48-bit Channel Link Serializer / Deserializer Evaluation Board 133MHz

Description:

The CLINK3V48BT-133 evaluation kit demonstrates the performance of the DS90CR485/485 48-bit, 66 - 133 MHz Channel Link SerDes chipset.

The transmitter serializes 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phase-locked clock is also transmitted in parallel with the data streams over a 9th LVDS pair. The receiver converts the 8 LVDS data streams plus clock back to 48 LVCMOS/LVTTL data bits plus clock.

Contents:

• CLINK3V485/486 PCB with DS90CR485VS Transmitter and DS90CR486VS Receiver
• One 2-meter 3M MDR LVDS cable interface
• Evaluation Kit Documentation
• DS90CR485/DS90CR486 Datasheet

What the user needs to provide:

The users need to provide 3.3V and/or a 2.5V supply. The device in this kit can be configured to generate its own LVDS data (PRBS-15 and PRBS-23). However, if users want to do BERT on the whole system, they will need to have equipment to send 24 bits of parallel DDR LVCMOS data + 1 Tx clock as well as receive 48 bits of parallel LVCMOS data + 1 Rx clock. If desired, users can use a Tx board from another CLINK kit to avoid using the DDR interface on the serializer in the CLINK3V48BT-133 kits.

• SerDes Evaluation Boards
• SerDes Feature Site