16-bit Bus LVDS SERDES Evaluation Board
DS92LV16 Product Folder
Description:
National Semiconductor's BLVDS16EVK evaluation board demonstrates the DS92LV16 BLVDS Serializer and Deserializer (SERDES) interface device. This evaluation board verifies the:
- Serializer block that serializes the 16-bit parallel bus into a serial stream with embedded clock,
- Deserializer block that deserializes the serial data stream into a 16-bit parallel bus with associated clock,
- The BLVDS driver's line driving capability across a short Z-pack cable.
The serializer accepts up to sixteen 3V LVTTL/LVCMOS data signals from an incoming data source along with the clock (TCLK) and then converts the parallel signals into a single serialized BLVDS data stream. The deserializer recovers the BLVDS serialized data stream and converts it back into parallel 3VLVTTL/LVCMOS data and clock output signals. Note that the DS92LV16 serializer block and the deserializer block can operate independently of each other. The device also includes several test modes. By enabling the LINE LOOPBACK (LINE_LE) function, the signal integrity of the link may be checked.
Contents:
What the user needs to provide:
Users will have to provide 3.3V power supply, 16 parallel LVCMOS data bits + 1 Tx clock, and a reference clock if they do not wish to operate at 50 MHz. If users wish to perform BERT, they will need equipment to receive 16 parallel LVCMOS data bits + 1 Rx clock. |
