10-Bit Bus LVDS Serializer / Deserializer Evaluation Board

Description:

This Bus LVDS demonstration board implements the National Semiconductor's DS92LV1021 Serializer and DS92LV1212A Deserializer Interface devices in a stand-alone pattern generator/checker test circuit.

The primary objective of the board is to verify operation of National Semiconductor's Bus LVDS SER/DES chipset over 100 ohm Category 5 unshielded twisted pair media, which is the same as used for Ethernet applications. Selection of either Random patterns or "DC Balanced"codes demonstrates reliability through direct and transformer coupling schemes. "DC Balanced" codes are those codes containing exactly 5 one's and 5 zeros, thereby presenting an overall zero bias in transformer coupled or capacitively coupled circuits.

The board may also be used as a prototyping vehicle for simple customer applications, such as attachment to A/D or D/A converters. To accomplish this, a wire-wrap prototyping area is provided with provisions to connect to the Bus LVDS chips and the MACH PLD.

Contents:

• BLVDS03 PCB with the DS92LV1021A Transmitter and the DS90LV1212A Receiver
• One 2-meter 3M MDR LVDS cable interface
• Evaluation Kit Documentation
• DS92LV1021A & DS92LV1212A Datasheet

What the user needs to provide:

• 3.3V supply
• 15-66 MHz clock source with TTL/LVCMOS levels

• AN-1909 - Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES
• AN-1238 - Application Note 1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices

• SerDes Evaluation Boards
• SerDes Feature Site