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Design Description
The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems. The subsystem includes the ADC16DV160 analog-to-digital converter (ADC), LMH6517 Digitally-controlled Variable-Gain Amplifier (DVGA) and LMK04031B precision clock conditioner.
In the signal path, the subsystem provides impedance-matched, single-to-differential conversion through a 1:4 transformer and a 31.5 dB amplification gain range in 0.5 dB steps through the DVGA. The anti-aliasing filter at the output of the DVGA provides noise filtering and over 40 dB harmonic suppression by selecting the 20 MHz signal band centered at 192 MHz. The signal is then sampled and quantized by the ADC into 16-bit words using a 153.6 MHz CMOS clock.
In the clock path, a LMK04031B clock conditioning circuit operates with a 61.44 MHz reference oscillator and 76.8 MHz VCXO to provide the 153.6 MHz CMOS sampling clock. The clock output is also filtered and buffered to provide very low broadband noise for less than 200 fs total jitter over the clock input bandwidth of the ADC.
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Design Resources
Additional Product Resources
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ADC16DV160
- Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs from the PowerWise@reg; Family |
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LMH6517
- Multi Standard, IF and Baseband, Dual, DVGA |
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LMK04031B
- Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.5 GHz VCO |
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LM2734
- Thin SOT23 1A Load Step-Down DC-DC Regulator |
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LP5900
- Ultra Low Noise, 150mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor |
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LP3878-ADJ
- Micropower 800mA Low Noise "Ceramic Stable" Adjustable Voltage Regulator for 1V to 5V Applications |
- datasheet
- application notes
- Webench Online design tools
- samples
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Board Photo
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Features
Key Features of the SP16160CH1RB High-IF Sub-Sampling Receiver Reference Design Board
- Demonstrates a high-IF sub-sampling subsystem architecture used in wireless infrastructure systems
- Configured for a 20 MHz input bandwidth centered at 192 MHz
- Configured with a low-noise, 153.6 MSPS CMOS sampling clock
- Featured Products Include:
- ADC16DV160 dual 16-bit, 160 Megasample per second (MSPS) ADC with parallel LVDS outputs
- LMH6517 Digitally-controlled, Variable Gain Amplifier (DVGA) with 31.5 dB gain range in 0.5 dB steps
- LMK04031B low-jitter precision clock conditioner consisting of cascaded phase locked loops (PLLs), an internal voltage controlled oscillator (VCO) and a distribution stage
- Several energy-efficient power management ICs
- Large-signal (-1 dBFS) performance for a 192 MHz input signal:
- SNR = 71 dBFS
- SFDR > 80 dBFS
- Small-signal (-6 dBFS) performance for a 192 MHz input signal:
- SNR = 72.7 dBFS
- SFDR > 92 dBFS
- 200 kHz channel performance for base-station receiver applications:
- SNR = 99 dBFS under normal conditions
- SNR = 94 dBFS under blocking conditions
- SFDR > 90dBFS under blocking conditions
- Total integrated jitter < 200 fs
- PIC Loader board included with reference board for quick and easy configuration of the LMK04031B
- Compatible with the WaveVision 5.1 Data Capture Board and WaveVision 5 software for simplified evaluation
- All internal register ADC and DVGA features can be exercised using the WaveVision 5 software
- Board comes fully assembled and tested
- Operates from a single (+5V) supply
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