Design Description

This reference design implements a High IF Receiver circuit that utilizes an LMH6515 DVGA and ADC14V155 Analog to Digital Converter (ADC). The design illustrates variable gain IF amplification and digitization in wireless infrastructure systems and frequency domain analyzers. This flexible subsystem provides excellent sensitivity for input signal frequencies up to 240 MHz. It achieves a small-signal SNR of 72 dBFS and a SFDR greater than 90 dBFS with a 169 MHz input frequency. Large signal performance yields a SNR of 68.3 dBFS and SFDR of 77 dBFS at 169 MHz. In addition to the LMH6515, the design includes National's ADC14V155 14-bit, 155 MSPS ADC with dual data rate, parallel LVDS outputs. The timing is provided by the LMK03001C low-jitter precision clock conditioner with an integrated voltage-controlled oscillator (VCO) that provides 190 femtosecond (fs) jitter over an integration bandwidth of 100 Hz to 20 MHz; as well as several energy-efficient power management ICs.

•	RD-146 Reference Design Document
•	Design Files (Schematic, Board Layout, Gerber, and BOM)

Additional Resources

Board Photo

ADC14V155KDRB High IF Receiver Reference Design Board

• Enables evaluation of a variable gain IF amplification and digitization subsystem with high dynamic range.
• Demonstrates a subsystem architecture used in many wireless infrastructure systems and frequency domain analyzers.
• Configured for an inut signal frequency of 169 MHz
• Provides excellent sensitivity for input signal frequencies up to 240 MHz
• Featured products include :
  • LMH6515: 450 MHz DVGA with from National Semiconductor's Powerwise® family
  • ADC14V155: 14-bit, 155 MSPS, 1.1 GHz input bandwidth ADC with parallel LVDS outputs from National Semiconductor's Powerwise® family
  • LMK03001C: low-jitter precision clock conditioner with an integrated voltage-controlled oscillator (VCO) from National Semiconductor's Powerwise® family provides 190 fs jitter (100 Hz to 20 MHz integration bandwidth
  • Several energy-efficient power management ICs from National Semiconductor
• Reference design performance for a 169 MHz input signal
  • Small-signal SNR of 72 dBFS and SFDR greater than 90 dBFS
  • Large signal SNR of 68.3 dBFS and SFDR of 77 dBFS

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