LM5000 Reference Design - Sepic Converter, No Transformer: 4-9V Input, 5V @ 0.6A Output

  Design Specifications

Inputs Outputs #1
VinMin=4.0 V Vout1=5.0 V
VinMax=9.0 V Iout1=0.6 A
   Design Resources

LM5000 Reference Design

  Additional Resources


LM5000 Product Folder
LM5000EVAL Evaluation Board
   Bill Of Materials

Part Manufacturer Part# Attributes
Cbp Vishay VJ0805Y104KXXAT 0.1u F
Cc1 Vishay VJ0805A101KXXAT 100p F
Cc2 Vishay VJ0805Y103KXXAT 0.01u F
Cin1 TDK C3225X5R1C106 10u F, 1m Ohms
Cin2 Vishay VJ0805Y104KXXAT 0.1u F
Co1 TDK C3216X5R0J106 10u F
Co2 Sanyo 16MV470WG 470u F, 0.11 Ohms
Cs TDK C3216X5R0J106 10u F
Css Vishay VJ0805Y104KXXAT 0.1u F
D1 ONSEMI MBRA120 0.34 V
L1 Coilcraft DO3316P-223 22.0u H, 0.05 Ohms
L2 Coilcraft DO3316P-223 22.0u H, 0.05 Ohms
Rc1 Vishay CRCW08051002FRT6 10k Ohms
Rf1 Vishay CRCW08051002FRT6 10k Ohms
Rf2 Vishay CRCW08053012FRT6 30.1k Ohms
U1 National Semiconductor LM5000

  Design Description

The LM5000 is used to design a SEPIC power supply with a positive input voltage rail that can go above or below output voltage rail. The LM5000 is a PWM regulator with internal FET switch which minimizes parts count and simplifies design. Typically the SEPIC architecture is used in order to take advantage of easily available inductors rather than less available transformers used for similar applications with flyback architecture.

During the ON-time of the switch the input voltage charges the L1 inductor. The negative voltage, relative to ground, across the SEPIC capacitor Cs charges the inductor L2. During the switch OFF-time both inductors discharge through D1 to the output. It is the average of this pulsed discharge current that forms the output load current and charges the output capacitors to the required voltage. Capacitor Css controls the softstart time and Cbp is used for bypassing purposes. Minimal ceramic capacitance, Cin1 and Cin2, is required on the input, while output capacitance is typically larger (Co2 is 470uF) due to the pulsed nature of the output current waveform. Transient compensation for the power supply loop is accomplished via the resistor and capacitor combination at the COMP pin of the regulator.



  Schematic

Example Schematic Showing Connection for all Components.


  Layout


Board's Bottom View


Board's Top View