Reliability Programs

National Semiconductor Corporation strives to achieve best-in-class quality and reliability performance on all their products through a systematic approach that emphasizes quality at every phase of product development through manufacturing. From initial design conception to fabrication, test, and assembly; quality is built-in and assured through stringent SPC monitoring of fabrication and assembly processes, materials inspections, wafer level reliability (WLR), new product qualifications, reliability monitoring of finished product and strict change control management.

What is Reliability?

Reliability is the characteristic expressed by the probability that the part will perform its intended function for a specific period of time under defined usage conditions.

Reliability Failures

There are 2 basic types of failures, Early Failures and Wear Out Failures. These are reflected in the curve known as the Bathtub curve.

National Semiconductor uses Reliability Testing to ensure all its products are below targets set for Early Failure Rates in PPM and Wear Out Failures in FITs.

Qualification

New Processes and New Packages

New Processes and New Packages are qualified using a minimum 3 lot (77 units per lot) testing for:

• Early Failure Testing (915 samples)
• Operating Life Test
• Temp and Humidity Biased Test
• Temperature Cycling
• Auto-Clave
• ESD/Latch-Up
• Board Level Temp Cycle (for packages)

Power Cycling and Data Retention Testing is also done when applicable.

Smart Quals

Products designed to Process and Package Design Rules and using Qualified Processes and Packages are released using 168hr Rel Data.
This approach supports Time to Market needs without compromising Reliability.
To ensure there is no customer risk, National has continuous reliability monitoring in place.

Reliability Monitor Program

An Ongoing Reliability Monitor is in place to ensure that products manufactured to Qualified Processes under Qualified Reliability Standards, has not drifted.

Results of the Rel Monitor Program are published on National’s Quality Web Page; Test Frequency is as posted below.

Fix Reliability Testing Capabilities Reliability Test Services and ESD and Latch-Up Testing Labs are fully equipped to support the Reliability Qualification Testing. Details of the Lab Equipment are listed in the following two tables. Reliability Testing Services Equipment Inventory

Equipment in the ESD/Latch-Up Lab

Failure Mechanisms/Failure Models

Various failure mechanisms are tested during Rel Testing. Major ones are listed below.

Failure Mechanism and Model

Determination of Failure Rate (Point Estimate)

Failure rate can be determined by using actual test results. Determine "demonstrated" failure rate from actual test data as follows:

Failure Rate=No. rejects/sample size x no. hours

Example 1. Assume a sample size of 13500, 2 failures and test duration of 500 hours. To calculate FR:

FR = 2 rejects/13500 devices x 500 hours
FR = 2/6750000 device-hours=0.000000296 rejects per device-hour
          296 FITS (reciprocal of 0.000000296)
          or 3375,000hours MTBF

In expressing Failure Rate, the equivalent values below may be helpful.

Determination of Failure Rate (Statistical Estimates)

In addition to point estimates, FR and MTBF may be estimated by using the chi-square statistic at 2 (r + 1) degrees of freedom. The 50% probability statistic would give the "best estimate", the 60% or 90% probability statistic would give the upper confidence limit.

Acceleration Factors

In order to express accelerated test results in terms of expected failure rate at actual use conditions, semiconductor manufacturers commonly use the Arrhenius model.

The Arrhenius model assumes that degradation of a performance parameter is linear with time, with the rate of degradation depending on the temperature stress. To put it another way, the Arrhenius equation relates the time rate of change of a process to the temperature at which the process is taking place.

If appropriate, the calculated acceleration factors listed in the following table may be used.

Acceleration Factors for Common Junction Temperatures
and Common Activation Energies

Calculation of Applicable Junction Temperature

Failure rates and MTBFs obtained from Operating Life Tests pertain when the junction temperature is the same as the ambient test temperature. Temperatures used during OPL tests are usually T_A=125°C or T_A=150°C. In most cases, these ambient temperatures are very close to the junction temperature T_J  . However, when a significant difference between T_A and T_J exists, respective T_J must be considered. This would be the case with parts that dissipate significant amounts of power, such as certain linear and MOS devices.

Confidence Factors

The failure rate resulting from a High Temperature Bias test is an average, or estimate, of the typical expected failure rate for a product or process; but has no statistical boundaries established.

National Semiconductor generally states the upper 60% confidence limit for failure rate estimate using the chi-squares statistic, per the following formula.

Values of chi square are found in a number of statistical tables. A few more typical values are shown as follows:

Percentiles of the Chi² Distribution
(Values of Chi² corresponding to certain selected probabilities)

Typical Use		AQL	Best Estimate	60% Confidence	LTPD or 90% Confidence
Probability in %		5.0	50.0	60.0	90.0
		0.05	0.50	0.60	0.90
df	Total Failures
2 4 6 8 10 12 14 16 18 20 22 26 32 42	0 1 2 3 4 5 6 7 8 9 10 12 15 20	0.103 0.711 1.640 2.730 3.940 5.230 6.570 7.960 9.390 10.900 12.800 15.400 20.100 28.200	1.390 3.360 5.350 7.340 9.340 11.300 13.300 15.300 17.300 19.300 21.300 25.300 31.300 41.300	1.830 4.040 6.210 8.350 10.500 12.600 14.700 16.800 18.900 21.000 23.000 27.200 33.400 43.700	4.61 7.78 10.60 13.40 16.00 18.50 21.10 23.50 26.00 28.40 30.80 35.60 42.60 54.10