Metrics: Reliability

Available Reports

PPM/FITS Summary: A graphical trend of National Semiconductor's Reliability Performance.

PPM/FITS - By Process: Failure Rates of Major Processes at National Semiconductor.

Package Data: Failure Rates of all Packages at National Semiconductor.

In reviewing this data, it may be helpful to refer to our Process by NSID Cross Reference Table (pdf: 1.8MB) and information on our Reliability Testing Programs.

Purpose of this Metric

• To provide a periodic monitor of product reliability under accelerated test conditions on wafer fabrication and assembly processes.
• To provide fab process and package reliability performance characteristics to customer.

Audit Strategy

• Package/Assembly processes are audited by Autoclave (ACLV), Temperature and Humidity Bias Test (THBT) and Temperature Cycling (TMCL) tests.
• Wafer fabrication processes are monitored by EFR and Long Term High Temperature Operating Life (OPL) tests.
• Devices are selected within each package and process audit groups based on representability and high manufacturing volume. Each audit group contains at least 3 devices.

Test Frequency

PPM/FITS Summary 

National Semiconductor conducts a Long Term Audit (LTA) program in order to identify trends in reliability of our products. The chart below displays the Early Failure Rate (PPM) and Long Term Life Failure Rate (FITS) trends for these products.

The Early Failure Rates were calculated as point estimates. Long Term Failure Rates (FITS) were calculated using activation energies of 0.7eV to derate the high temperature accelerated OPL test data to application junction temperatures of 55°C and were calculated with 60% confidence intervals.

The trend lines for both PPM and FIT rates illustrate the positive year to year reliability improvements at National Semiconductor.

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PPM/FITS by Process 

The following table lists Early Failure Rates in parts per million (PPM ) and Long Term Failure Rates in units per billion device hours (FITS) for the wafer fabrication processes.

The Early Failure Rates were calculated as point estimates. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the stress temperature to an application temperature of 55°C.

The data used to calculate the failure rates was obtained from OPL tests performed in the Reliability Monitoring Program.

These failure rates are updated quarterly with data through the end of the preceding quarter.

Period Covered: 29th Feb 2004 to 24th Feb 2008

Last Updated: 16th August 2008

Process	EFR	Sample Size	*PPM	Rejects	Device Hours	FITS	MTTF
.35	0	17125	0	0	1155000	4	327734403
.5	0	9960	0	0	797500	5	226292802
ABCD150	0	28280	0	0	2974000	2	843880620
ABIC	0	13658	0	0	2198000	2	623688501
BICMOS8	2	10333	194	0	1227500	0	348306476
BIFET	0	10895	0	0	795000	5	225583420
CBIC	0	6795	0	0	1065000	4	302196657
CMOS	0	16925	0	0	2065000	2	585949388
CMOS7	0	13906	0	0	862500	5	244736730
CMOS8	1	10575	95	0	1072500	4	304324803
CMOS8T	0	13785	0	0	1420000	3	402928877
CMOS9	1	4942	203	0	720500	5	204443842
CS065	1	26215	39	0	2917000	2	827706714
CS080	0	26305	0	0	2188500	2	620992850
CS100	1	12726	39	0	673000	6	190965587
CS150	1	10260	98	0	797500	5	226292802
CS200*	0	9850	0	0	3375000	2	957665465
DLM	0	7505	0	0	1180000	3	334828221
HV700	0	13625	0	0	1222500	3	346887713
LB250	0	17125	0	0	1525000	3	432722913
LB300	0	30674	0	0	3046500	2	864452693
LFAST1	0	16945	0	0	1930000	2	547642769
LMDMOS	0	15190	0	0	1750000	3	496567278
LS JI SLM*	0	800	0	0	100000	36	28375273
P2CMOS	0	45010	0	1	3767500	3	484371054
PVIP050	0	8430	0	0	495000	8	140457601
RFCMOS	0	2055	0	0	370000	10	104988510
SLM	0	39546	0	0	2857500	2	810823427
TS060D	0	7564	0	0	522500	7	148260801
TS100	0	5220	0	0	675000	6	191533093
VIP 10	0	10415	0	0	840000	5	238352293
VIP III	0	13100	0	0	987500	4	280205821
VIP III H/HU2	0	2366	0	0	567554	7	161044997
VIP1+	0	18700	0	0	2065000	2	585949388

Note: PPM is a point estimate based on rejects and sample size for EFR.
* - Data from previous time range 02/24/2003 - 02/27/2004

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Package Data - Reliability Monitor Plan 

The following tables list failure rate in percentage (PCT) for packages. The data used to calculate the failure percentage was obtained from ACLV, THBT and TMCL tests.

These tables are updated quarterly with data through the end of the preceding quarter.

Percentage = Rejects/Sample size * 100
Period Covered: 29th Feb 2004 to 24th Feb 2008
Last Updated: 27 August 2008

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