SCANSTA112 - 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Datasheet Packaging Samples & Pricing Eval. Boards Reliability Models Application Notes Knowledge Base

Features
True IEEE 1149.1 hierarchical and multidrop addressable capability
The 8 address inputs support up to 249 unique slot addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved)
7 IEEE 1149.1-compatible configurable local scan ports
Bi-directional Backplane and LSP0 ports are interchangeable slave ports
Capable of ignoring TRST# of the backplane port when it becomes the slave.
Stitcher Mode bypasses level 1 and 2 protocols
Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three
Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port
General purpose local port pass through bits are useful for delivering write pulses for Flash programming or monitoring device status.
Known Power-up state
TRST# on all local scan ports
32-bit TCK counter
16-bit LFSR Signature Compactor
Local TAPs can become TRI-STATE via the OE# input to allow an alternate test master to take control of the local TAPs (LSP0-3 have a TRI-STATE notification output)
3.0-3.6V VCC Supply Operation
Supports live insertion/withdrawal

General Description


The SCANSTA112 extends the IEEE Std. More...


  Typical Application
*click for larger image


Parametric Table     expand
Parametric Table    collapse
Temperature Min -40 deg C
Temperature Max 85 deg C
Temperature Min -40 deg C
Temperature Max 85 deg C
View Using Catalog

  Additional Resources
Application Notes (see below)


Block Diagram


*click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to View Online Click link below to Download Click link below to Receive via Email
SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer 692 Kbytes 20-Oct-05 View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
SCANSTA112EVK7-port Multidrop IEEE 1149.1 (JTAG) MultiplexerPreliminaryN/A
 
Buy Now
1+$195.001-
N/AN/A
SCANSTA112SMFBGA100STD
NOPB
3
4
235
260
RoHS Download Full production
sta112sm.ibs
Samples
Buy Now
1K+$5.70tray
of
240
NSUZXYTT
SCANSTA112
SM
8 weeks1000
SCANSTA112SMXFBGA100STD
NOPB
3
4
235
260
RoHS Download Full production
sta112sm.ibs
 
Buy Now
1K+$5.70reel
of
1000
NSUZXYTT
SCANSTA112
SM
8 weeks2000
SCANSTA112VSTQFP100STD
NOPB
2
2
235
260
RoHS Download Full production
sta112sv.ibs
Samples
Buy Now
1K+$5.70tray
of
90
NSUZXYYTT
SCANSTA112
VS
8 weeks500
SCANSTA112VSXTQFP100STD
NOPB
2
2
235
260
RoHS Download Full production
sta112sv.ibs
 
Buy Now
1K+$5.70reel
of
1000
NSUZXYYTT
SCANSTA112
VS
8 weeks2000

General Description


The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

Reliability Metrics


Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
SCANSTA112SMCMOS7013906008625005244736730
SCANSTA112SMXCMOS7013906008625005244736730
SCANSTA112VSCMOS7013906008625005244736730
SCANSTA112VSXCMOS7013906008625005244736730

For more information on Reliability Metrics, please click here.


Application Notes


TitleSize in Kbytes Date Click link below to View Online Click link below to Download Click link below to Receive via Email
AN-1327: Application Note 1327 Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux 64 Kbytes 2-Sep-04 View Online Download Receive via Email
AN-1340: Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux 441 Kbytes 13-Jul-05 View Online Download Receive via Email
AN-1340 (Chinese): Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux
234 Kbytes  
AN-1312: Application Note 1312 Scan Bridge (STA111/STA112) Timing 41 Kbytes 7-Jun-04 View Online Download Receive via Email
AN-1312 (Chinese): Application Note 1312 Scan Bridge (STA111/STA112) Timing
138 Kbytes  
AN-1259: Application Note 1259 SCANSTA112 Designers Reference 533 Kbytes 7-Aug-08 View Online Download Receive via Email

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[Information as of 29-Aug-2008]