Features • True IEEE 1149.1 hierarchical and multidrop addressable capability • The 8 address inputs support up to 249 unique slot addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) • 7 IEEE 1149.1-compatible configurable local scan ports • Bi-directional Backplane and LSP0 ports are interchangeable slave ports • Capable of ignoring TRST# of the backplane port when it becomes the slave. • Stitcher Mode bypasses level 1 and 2 protocols • Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three • Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port • General purpose local port pass through bits are useful for delivering write pulses for Flash programming or monitoring device status. • Known Power-up state • TRST# on all local scan ports • 32-bit TCK counter • 16-bit LFSR Signature Compactor • Local TAPs can become TRI-STATE via the OE# input to allow an alternate test master to take control of the local TAPs (LSP0-3 have a TRI-STATE notification output) • 3.0-3.6V VCC Supply Operation • Supports live insertion/withdrawal Description The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

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Typical Application *click for larger image	Block Diagram *click for larger image

Datasheets

Title		Size	Date	Other Language
	SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer	692 Kbytes	20-Oct-05

Featured Application Notes

Title		Size	Date	Other Language
	AN-1312: Application Note 1312 Scan Bridge (STA111/STA112) Timing	41 Kbytes	7-Jun-04	中文
	AN-1259: Application Note 1259 SCANSTA112 Designer`s Reference	687 Kbytes	5-Jan-10	中文
	AN-1340: Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux	179 Kbytes	17-Dec-09	中文
	AN-1327: Application Note 1327 Simplified Programming of Altera FPGAs Using a SCANSTA111/112 JTAG Scan Chain Mux	180 Kbytes	17-Dec-09

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Standard Pack Size
SCANSTA112SM/NOPB SCANSTA112SM RoHS Status	FBGA	Full production Lead Time: 6 weeks	Distributor Region Qty ARROW Worldwide 240 AVNET-EM Worldwide 385 DIGIKEY Worldwide 189 FUTURE Worldwide 240 NEWARK Americas 235	$5.70 each at 1K+ pcs	tray of 240
SCANSTA112SMX/NOPB SCANSTA112SMX RoHS Status	FBGA	Full production Lead Time: 8 weeks	Distributor Region Qty AVNET-EM Worldwide 1000 DIGIKEY Worldwide 0	$5.70 each at 1K+ pcs	reel of 1000
SCANSTA112VS/NOPB SCANSTA112VS RoHS Status	TQFP	Full production Lead Time: 8 weeks	Distributor Region Qty ARROW Worldwide 97 AVNET-EM Worldwide 197 DIGIKEY Worldwide 28 FUTURE Worldwide 917 NEWARK Americas 147	$5.70 each at 1K+ pcs	tray of 90
SCANSTA112VSX/NOPB SCANSTA112VSX RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty DIGIKEY Worldwide 0	$5.70 each at 1K+ pcs	reel of 1000

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/packaging/leadfree.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/quality/green.

National's certificate of product compliance is located at RoHS Status.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/packaging/leadfree.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/quality/green.

National's certificate of product compliance is located at RoHS Status.

Design Tools

Title	Size	Date
SCANSTA112 Quick Reference Guide	87 Kbytes	26-Jan-2010

CAD Symbols and Models Download SCANSTA112 CAD Symbols

Models sta112sm.ibs

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
SCANSTA112SM	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA112SMX	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA112VS	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA112VSX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/packaging/leadfree.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/quality/green.

National's certificate of product compliance is located at RoHS Status.