| • | True IEEE 1149.1 hierarchical and multidrop addressable capability |
| • | The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) |
| • | 3 IEEE 1149.1-compatible configurable local scan ports |
| • | Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three |
| • | Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port |
| • | LSP ACTIVE outputs provide local port enable signals for analog busses supporting IEEE 1149.4. |
| • | General purpose local port passthrough bits are useful for delivering write pulses for FPGA programming or monitoring device status. |
| • | Known Power-up state |
| • | TRST# on all local scan ports |
| • | 32-bit TCK counter |
| • | 16-bit LFSR Signature Compactor |
| • | Local TAPs can become TRI-STATE via the OE# input to allow an alternate test master to take control of the local TAPs (LSP0-2 have a TRI-STATE notification output) |
| • | 3.0-3.6V VCC Supply Operation |
| • | Power-off high impedance inputs and outputs |
| • | Supports live insertion/withdrawal |
RoHS Compliance Information
