Features • True IEEE 1149.1 hierarchical and multidrop addressable capability • The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) • 3 IEEE 1149.1-compatible configurable local scan ports • Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three • Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port • LSP ACTIVE outputs provide local port enable signals for analog busses supporting IEEE 1149.4. • General purpose local port passthrough bits are useful for delivering write pulses for FPGA programming or monitoring device status. • Known Power-up state • TRST# on all local scan ports • 32-bit TCK counter • 16-bit LFSR Signature Compactor • Local TAPs can become TRI-STATE via the OE# input to allow an alternate test master to take control of the local TAPs (LSP0-2 have a TRI-STATE notification output) • 3.0-3.6V VCC Supply Operation • Power-off high impedance inputs and outputs • Supports live insertion/withdrawal Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

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Datasheet

Title		Size	Date	Other Language
	SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port	917 Kbytes	20-Oct-05

Featured Application Notes

Title		Size	Date	Other Language
	AN-1312: Application Note 1312 Scan Bridge (STA111/STA112) Timing	41 Kbytes	7-Jun-04	中文
	AN-1340: Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux	441 Kbytes	13-Jul-05	中文
	AN-1327: Application Note 1327 Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux	64 Kbytes	2-Sep-04
	AN-1259: Application Note 1259 SCANSTA112 Designers Reference	533 Kbytes	7-Aug-08	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
SCANSTA111MT	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA111MTX	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA111SM	CMOS7	0	18406	0	0	1089000	4	309006723
SCANSTA111SMX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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