National Semiconductor | High-performance Analog

 

 SCANSTA101   

Low Voltage IEEE 1149.1 System Test Access (STA) Master
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Features

  • Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
  • Supported by National's SCAN Ease (SCAN Embedded Application Software Enabler) Software Rev 2.0
  • Uses generic, asynchronous processor interface; compatible with a wide range of processors and processor clock (PCLK) frequencies
  • 16-bit data interface (IP scalable to 32-bit)
  • 2k x 32 bit dual-port memory
  • Load-on-the-fly (LotF) and Preloaded vector operating modes supported
  • On-Board Sequencer allows multi-vector operations such as those required to load data into an FPGA
  • On-Board Compares support Test Data In (TDI) validation against preloaded expected data
  • 32-bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) port for signature compression
  • State, Shift, and BIST macros allow predetermined Test Mode Select (TMS) sequences to be utilized
  • Operates at 3.3 V supply voltages with 5 V tolerant I/O
  • Outputs support Power-Down TRI-STATE mode.
  • Description

    The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a stand-alone boundary scan tester.

    The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100. The SCANSTA101 supports the IEEE 1149.1 Test Access Port (TAP) standard and the IEEE 1532 standard for in-system configuration of programmable devices.

    The SCANSTA101 improves test vector throughput and reduces software overhead in the system processor. The SCANSTA101 presents a simple, register-based interface to the system processor. National Semiconductor Corporation provides C-language source code which can be included in the embedded system software. The combination of the SCANSTA101 and its support software comprises a simple API for boundary scan operations.

    The interface from the SCANSTA101 to the system processor is implemented by reading and writing registers, some of which map to locations in the SCANSTA101 memory. Hardware handshaking and interrupt lines are provided as part of the processor interface.

    The SCANSTA101 is available as a stand-alone device packaged in a 49-pin BGA package. It is also available as an IP macro for synthesis in programmable logic devices.

    Also Recommended
    SCANSTA1127 Port Addressable JTAG Multiplexor

    Parameters / ValuesSCANSTA101 SCANSTA112
    Temperature Min-40 deg C -40 deg C
    Temperature Max85 deg C 85 deg C

    Datasheets
    TitleSizeDateOther
    Language
    SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master681
    Kbytes
    1-Jun-10   


    Other Technical Documents
    TitleTypeDate
    JTAG Advanced Capabilities and System DesignSignal Path Designer 2009-03-19
    SCANSTA101 Quick Reference GuideApp Note 2010-01-07

    Part Number(s)
    (NSID)
    Top ViewAvailabilityCurrent Reported StockBudgetary PricingPack
    Size
    SCANSTA101SM/NOPB

    SCANSTA101SM

    RoHS Status


    FBGA
    Full production
    Lead Time: 6 weeks

    Samples
    DistributorRegionQty
    AVNET-EMWorldwide760
    CEACAsia Pacific416
    DIGI-KEYWorldwide0
    FARNELLEurope and Asia4
    $8.50 each at 1K+ pcstray
    of
    416
    SCANSTA101SMX/NOPB

    SCANSTA101SMX

    RoHS Status


    FBGA
    Full production
    Lead Time: 6 weeks

     
    DistributorRegionQty
    DIGI-KEYWorldwide0
    $8.50 each at 1K+ pcsreel
    of
    2000

    All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

    Moisture Sensitivity Level Data for SCANSTA101.

    A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

    National's certificate of product compliance for SCANSTA101 is located at RoHS Status.

    Part Number(s)
    (NSID)
    Weight
    (milligrams)
    TypePinsMSL RatingPeak ReflowRoHS
    Status
    CAD SymbolsModelsPackage
    Marking
    Format
    SCANSTA101SM/NOPB

    SCANSTA101SM
    120.419
    122.75
    FBGA494
    3
    260
    235
    DetailDownload
    ibis file
    NSUZXYTTE#
    SCANSTA101
    SM
    SCANSTA101SMX/NOPB

    SCANSTA101SMX
    120.419
    122.75
    FBGA494
    3
    260
    235
    DetailDownload
    ibis file
    NSUZXYTT
    SCANSTA101
    SM

    All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

    Moisture Sensitivity Level Data for SCANSTA101.

    A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

    National's certificate of product compliance for SCANSTA101 is located at RoHS Status.

    Reliability Metrics
    Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
    SCANSTA101SMCMOS70213010015840003449464325
    SCANSTA101SMXCMOS70213010015840003449464325

    Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

    For more information on Reliability Metrics, please click here.


    All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

    Moisture Sensitivity Level Data for SCANSTA101.

    A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

    National's certificate of product compliance for SCANSTA101 is located at RoHS Status.

    [Information as of 9-Feb-2012]