Features • 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps total throughput • 8-level selectable pre-emphasis on each channel drives lossy cables and backplanes • >15kV HBM ESD protection on Bus LVDS I/O pins • Robust BLVDS serial data transmission with embedded clock for exceptional noise immunity and low EMI • Power saving control pin for each channel • IEEE 1149.1 "JTAG" Compliant • At-Speed BIST - PRBS generation • No external coding required • Internal PLL, no external PLL components required • Single +3.3V power supply • Low power: 260 mW (typ) per channel at 66 MHz with PRBS-15 pattern • Single 3.3 V supply • Fabricated with advanced CMOS process technology • Industrial -40 to +85°C temperature range • Compact 100-ball FBGA package Description The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew. Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used. The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity

MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST	629 Kbytes	5-Nov-04

Featured Application Notes

Title		Size	Date	Other Language
	AN-1376: Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs	1758 Kbytes	2-May-05
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04

Design Tools

Title	Size	Date
See the 18-bit SerDes Design Guide	2886 Kbytes	29-Mar-2007
"LVDS-18B-EVK for Pricing Information, see the DS92LV18 Product Folder"

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
SCAN921821TSM	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.