Features
Exceeds LV and HV CPRI voltage and jitter requirements
2457.6, 1228.8, and 614.4 Mbps operation
Integrated delay calibration measurement (DCM) directly measures T14 and Toffset delays to
≤ ± 800 ps
DCM also measures chip and other delays to
≤ ± 1200 ps accuracy
Deterministic chip latency
Independent transmit and receive PLLs for seamless RE synchronization
Low noise recovered clock output
Requires no jitter cleaning in single-hop applications
>8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV CDM
Hot plug protection
LOS, LOF, 8b/10b line code violation, comma, and receiver PLL lock reporting
Programmable hyperframe length and start of hyperframe character
Programmable transmit de-emphasis and receive equalization with on-chip termination
Advanced testability features
IEEE 1149.1 and 1149.6
At-speed BIST pattern generator/verifier
Multiple loopback modes
1.8V or 3.3V compatible parallel bus interface
100-pin TQFP package with exposed dap
Industrial –40 to +85° C temperature range
Description The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps serializer/deseralizer (SerDes) for high-speed bidirectional serial data
transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. The SCAN25100 integrates precision
delay calibration measurement (DCM) circuitry that measures link delay components to better than ± 800 ps accuracy.
The SCAN25100 features independent transmit and receive PLLs, on-chip oscillator, and intelligent clock management circuitry
to automatically perform remote radio head synchronization and reduce the cost and complexity of external clock networks.
The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable transmitter de-emphasis,
receiver equalization, speed rate selection, internal pattern generation/verification, and loop back modes. In addition to
at-speed BIST, the SCAN25100 includes IEEE 1149.1 and 1149.6 testability.
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