Features • Adjustable VOUT range of 0.80V to 1.8V • Wide VBIAS Supply operating range of 3.0V to 5.5V • Stable with 10µF Ceramic capacitors • Dropout voltage of 115 mV (typical) at 800 mA load current • Precision VADJ across all line and load conditions: • ±1.5% VADJ for TJ = 25°C • ±2.0% VADJ for 0°C ≤ TJ ≤ +125°C • ±3.0% VADJ for -40°C ≤ TJ ≤ +125°C • Over-Temperature and Over-Current protection • Available in 8 lead PSOP, 7 lead TO-220 and 7 lead TO-263 packages • −40°C to +125°C Operating Junction Temperature Range Description The LP38851-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the N-MOS power transistor, while VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The part is available in PSOP 8–pin, TO-220 7–pin, and TO-263 7-pin packages. Dropout Voltage: 115 mV (typical) at 800 mA load current. Low Ground Pin Current: 10 mA (typical) at 800 mA load current. Soft-Start: Programmable Soft-Start time. Precision ADJ Voltage: ±1.5% for TJ = 25°C, and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions Applications • ASIC Power Supplies in: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers • Server Core and I/O Supplies • DSP and FPGA Power Supplies • SMPS Post-Regulator

Also Recommended LP38852▲ 1.5A Version LP38853▲ 3A Version LP38851-ADJ Typical Application Circuit MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image LP38851-ADJ Typical Application Circuit	Block Diagram *click for larger image LP38851-ADJ Block Diagram
Typical Performance *click for larger image Ultra-Low Dropout Performance

Datasheet

Title		Size	Date	Other Language
	LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start	443 Kbytes	26-Jun-07	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1457: Application Note 1457 LP3884X-ADJ Evaluation Board	431 Kbytes	16-Jun-06

More Application Notes

Title		Size	Date	Other Language
	AN-1560: Application Note 1560 LP38852MR-ADJ Evaluation Board	280 Kbytes	17-Mar-07	中文
	AN-1479: Application Note 1479 LP38856S-1.2 Evaluation Board	468 Kbytes	3-Nov-06	中文
	AN-1504: Application Note 1504 LP38853S-ADJ Evaluation Board	573 Kbytes	13-Mar-07	中文
	AN-1480: Application Note 1480 LP38859S-1.2 Evaluation Board	522 Kbytes	3-Nov-06	中文
	AN-1815: Application Note 1815 LDOs Ease the Stress of Start-Up	149 Kbytes	23-Sep-08

Design Tools

Title	Size	Date
Article - How to Power Sub-Micron CMOS Loads with an Efficient LDO

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LP38851MR-ADJ	CS065	2	38968	52	0	4402000	1	1249079519
LP38851MRX-ADJ	CS065	2	38968	52	0	4402000	1	1249079519
LP38851S-ADJ	CS065	2	38968	52	0	4402000	1	1249079519
LP38851SX-ADJ	CS065	2	38968	52	0	4402000	1	1249079519
LP38851T-ADJ	CS065	2	38968	52	0	4402000	1	1249079519

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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