Features Quadruple Modulus Prescalers for Lower Divide RatiosAdvanced Delta Sigma Fractional CompensationFeatures for Improved Lock Times and ProgrammingWide Operating RangeUseful Features • RF PLL: 8/9/12/13 or 16/17/20/21 • IF PLL: 8/9 or 16/17 • 12 bit or 22 bit selectable fractional modulus • Up to 4th order programmable delta-sigma modulator • Fastlock / Cycle slip reduction • Integrated time-out counter • Single word write to change frequencies with Fastlock • LMX2485 RF PLL: 500 MHz to 3.0 GHz • LMX2485E RF PLL: 50 MHz to 3.0 GHz • Digital lock detect output • Hardware and software power-down control • On-chip crystal reference frequency doubler. • RF phase comparison frequency up to 50 MHz • 2.5 to 3.6 volt operation with ICC = 5.0 mA at 3.0 V Description The LMX2485 is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. The device is fabricated using National Semiconductor’s advanced process. With delta-sigma architecture, fractional spurs at lower offset frequencies are pushed to higher frequencies outside the loop bandwidth. The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the modulator order. Unlike analog compensation, the digital feedback technique used in the LMX2485 is highly resistant to changes in temperature and variations in wafer processing. The LMX2485 delta-sigma modulator is programmable up to fourth order, which allows the designer to select the optimum modulator order to fit the phase noise, spur, and lock time requirements of the system. Serial data for programming the LMX2485 is transferred via a three line high speed (20 MHz) MICROWIRE interface. The LMX2485 offers fine frequency resolution, low spurs, fast programming speed, and a single word write to change the frequency. This makes it ideal for direct digital modulation applications, where the N counter is directly modulated with information. The LMX2485 is available in a 24 lead 4.0 X 4.0 X 0.8 mm LLP package. Applications • Cellular phones and base stations • CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC • Direct digital modulation applications • Satellite and cable TV tuners • WLAN Standards

LMX2485 WEBENCH® Design/Analyze/Build It RF-Side PLL Design Options Min Output Freq MHz >= 500 help Max Output Freq MHz <= 3000 help Channel Spacing KHz > 0 help AUX-Side PLL Design Options Min Output Freq MHz >= 75 help Max Output Freq MHz <= 800 help Channel Spacing KHz > 0 help Global Design Options Crystal Frequency MHz > 0 help Max Supply V > 0 help What is WEBENCH®? Also Recommended LMX2485E▲ Extended Minimum Operating Frequency Down To 50 MHz. LMX2486▲ 4.5 GHz Maximum Operating Frequency. LMX2487▲ 6.0 GHz Maximum Operating Frequency. LMX2487E▲ 7.5 GHz Maximum Operating Frequency. MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	LMX2485/LMX2485E 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizers with 800 MHz Integer PLL	763 Kbytes	27-Feb-08	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1879: Application Note 1879 Fractional N Frequency Synthesis	511 Kbytes	10-Dec-08
	AN-1865: Application Note 1865 Frequency Synthesis and Planning for PLL Architectures	151 Kbytes	6-Feb-09

More Application Notes

Title		Size	Date	Other Language
	AN-1879: Application Note 1879 Fractional N Frequency Synthesis	511 Kbytes	10-Dec-08

Design Tools

Title	Size	Date
LMX2485 with Active Filter Using LM6211	1044 Kbytes	3-Nov-2006
LMX2485 Evaluation Board Instructions	1146 Kbytes	6-Feb-2006

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMX2485SQ	BICMOS8	2	14113	142	0	1677500	3	475995205
LMX2485SQX	BICMOS8	2	14113	142	0	1677500	3	475995205

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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