Features Unless otherwise noted, typical values at VS = 5V. Input offset voltage (LMP7707) ±200 µV (max) Input offset voltage (LMP7708/LMP7709) ±220 µV (max) Input bias current ±200 fA Input voltage noise 9 nV/ √Hz CMRR 130 dB Open loop gain 130 dB Temperature range −40°C to 125°C Gain bandwidth product (AV =10) 14 MHz Stable at a gain of 10 or higher Supply current (LMP7707) 715 µA Supply current (LMP7708) 1.5 mA Supply current (LMP7709) 2.9 mA Supply voltage range 2.7V to 12V Rail-to-rail input and output Description The LMP7707/LMP7708/LMP7709 devices are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers which each have a CMOS input stage and a wide supply voltage range. The LMP7707/LMP7708/LMP7709 are part of the LMP precision amplifier family and are ideal for sensor interface and other instrumentation applications. These decompensated amplifiers are stable at a gain of 6 and higher. The guaranteed low offset voltage of less than ±200 µV along with the guaranteed low input bias current of less than ±1 pA make the LMP7707/LMP7708/LMP7709 ideal for precision applications. The LMP7707/LMP7708/LMP7709 are built utilizing VIP50 technology, which allows the combination of a CMOS input stage and a supply voltage range of 12V with rail-to-rail common mode voltage capability. The LMP7707/LMP7708/LMP7709 are the perfect choice in many applications where conventional CMOS parts cannot operate due to the voltage conditions. The unique design of the rail-to-rail input stage of each of the LMP7707/LMP7708/LMP7709 significantly reduces the CMRR glitch commonly associated with rail-to-rail input amplifiers. Both sides of the complimentary input stage have been trimmed, thereby reducing the difference between the NMOS and PMOS offsets. The output swings within 40 mV of either rail to maximize the signal dynamic range in applications requiring low supply voltage. The LMP7707 is offered in the space saving 5-Pin SOT23 and 8-pin SOIC package, the LMP7708 is offered in the 8-Pin MSOP and 8-pin SOIC package and the quad LMP7709 is offered in the 14-Pin TSSOP and the 14-pin SOIC package. These small packages are ideal solutions for area constrained PC boards and portable electronics. Applications • High impedance sensor interface • Battery powered instrumentation • High gain amplifiers • DAC buffer • Instrumentation amplifier • Active filters

Also Recommended LMP7707▲ Single Version LMP7709▲ Quad Version Cap Load Isolation MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image Cap Load Isolation	Block Diagram *click for larger image
Typical Performance *click for larger image Open Loop Unity-Gain Stable vs. Decompensated

Datasheet

Title		Size	Date	Other Language
	LMP7707/LMP7708/LMP7709 Precision, CMOS Input, RRIO, Wide Supply Range Decompensated Amplifiers	1574 Kbytes	30-Jul-08	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1738: Application Note 1738 551013276 and 551013277 Evaluation Boards for Dual Decompensated Operational Amplifiers (MSOP-8 and SOIC-8)	323 Kbytes	12-Dec-07	日本語

More Application Notes

Title		Size	Date	Other Language
	AN-1515: Application Note 1515 A Comprehensive Study of the Howland Current Pump	227 Kbytes	29-Jan-08
	AN-1559: Application Note 1559 Practical RTD Interface Solutions	215 Kbytes	10-Oct-07	日本語 中文
	AN-1841: Application Note 1841 LMH1982 Evaluation Board User Guide	913 Kbytes	21-May-08	中文

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMP7708MA	VIP50CLZ3	0	1755	0	0	315000	12	89382110
LMP7708MAX	VIP50CLZ3	0	1755	0	0	315000	12	89382110
LMP7708MM	VIP50CLZ3	0	1755	0	0	315000	12	89382110
LMP7708MME	VIP50CLZ3	0	1755	0	0	315000	12	89382110
LMP7708MMX	VIP50CLZ3	0	1755	0	0	315000	12	89382110

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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