RoHS Compliance Information	Size in Kbytes	Date
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs	1228 Kbytes	1-Jul-09	Download

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$US each

LMK04033BEVAL

Clock Jitter Cleaner With Cascaded PLLs and Integrated 2.0 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)

Full production

N/A

1+

$320.00

1

-

N/A

N/A

LMK04033BISQE

LLP

48

NOPB

3

260

RoHS

N/A

Full production

N/A

1K+

$14.50

reel of 250

NS UZXYTT K04033BI

12 weeks

N/A

LMK04033BISQ

LLP

48

NOPB

3

260

RoHS

N/A

Full production

N/A

1K+

$14.50

reel of 1000

NS UZXYTT K04033BI

12 weeks

N/A

LMK04033BISQX

LLP

48

NOPB

3

260

RoHS

N/A

Full production

N/A

1K+

$14.50

reel of 2500

NS UZXYTT K04033BI

12 weeks

N/A

General Description

The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

Design Tools

Title	Size in Kbytes	Date
Evaluation Board Instructions	1416 Kbytes	16-Jun-2009	View Online	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

Title	Size in Kbytes	Date
AN-1734: Application Note 1734 Using the LMK03000C to Clean Recovered Clocks	188 Kbytes	2-May-08	Download
AN-1734 (Chinese): Application Note 1734 Using the LMK03000C to Clean Recovered Clocks	338 Kbytes
AN-1821: Application Note 1821 CPRI Repeater System	1497 Kbytes	15-May-08	Download
AN-1864: Application Note 1864 Phase Synchronization with Multiple Devices and Frequencies	150 Kbytes	24-Jun-08	Download
AN-1865: Application Note 1865 Frequency Synthesis and Planning for PLL Architectures	151 Kbytes	6-Feb-09	Download
AN-1910: Application Note 1910 LMK04000 Family Phase Noise Characterization	6740 Kbytes	15-Jan-09	Download