Features Cascaded PLLatinum PLL Architecture PLL1 Phase detector rate of up to 40 MHz Integrated Low-Noise Crystal Oscillator Circuit Dual redundant input reference clock with LOS PLL2 Normalized [1 Hz] PLL noise floor of -224 dBc/Hz Phase detector rate up to 100 MHz Input frequency-doubler Integrated Low-Noise VCO Ultra-Low RMS Jitter Performance 150 fs RMS jitter (12 kHz – 20 MHz) 200 fs RMS jitter (100 Hz – 20 MHz) LVPECL/2VPECL, LVDS, and LVCMOS outputs Support clock rates up to 1080 MHz Default Clock Output (CLKout2) at power up Five dedicated channel divider and delay blocks Pin compatible family of clocking devices Industrial Temperature Range: -40 to 85 °C 3.15 V to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Description The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance. The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1. The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

Also Recommended LMK01000 Distribution, Divide, And Delay Only LMK02000▲ Includes PLL For Use With External VCO/VCXO. LMK03200▲ 0-delay Outputs With PLL+VCO For Jitter Cleaning And Clock Generation Apps Diagram

Typical Application *click for larger image Apps Diagram	Block Diagram click for larger image Functional Block Diagram
Typical Performance *click for larger image Typical LVPECL PN (Typical Characteristics)

Parameters / Values	LMK04031	LMK02000	LMK03200
Max Output Clock Freq	785 MHz	800 MHz	1296 MHz
Min VCO Freq	1430 MHz	Undefined MHz	1185 MHz
Max VCO Freq	1570 MHz	Undefined MHz	1296 MHz
PLL Type	Cascaded PLLs + VCO	PLL only	PLL + VCO
RMS Jitter	0.15 ps	0.2 ps	0.8 ps
LVDS Outputs	2	3	3
LVPECL Outputs	2	5	5
LVCMOS Outputs	2	0	0
Min Supply Voltage	3.15 Volt	3.15 Volt	3.15 Volt
Max Supply Voltage	3.45 Volt	3.45 Volt	3.45 Volt
Temperature Min	-40 deg C	-40 deg C	-40 deg C
Temperature Max	85 deg C	85 deg C	85 deg C
PowerWise	Yes	Yes	No

Datasheets

Title		Size	Date	Other Language
	LMK04031 Low-Noise Clock Jitter Cleaner with Cascaded PLLs	1226 Kbytes	19-Sep-11

Application Notes

Title		Size	Date	Other Language
	AN-1942: Application Note 1942 LMH6517 Evaluation Board	3540 Kbytes	1-Dec-09
	AN-1950: Application Note 1950 Silently Powering Low Noise Applications	3415 Kbytes	28-Jul-09
	AN-1910: Application Note 1910 LMK04000 Family Clock Output Phase Noise Characterization with Multiple Voltage Controlled Oscillators	6740 Kbytes	15-Jan-09	中文
	AN-1939: Application Note 1939 Crystal Based Oscillator Design with the LMK04000 Family	2589 Kbytes	13-Mar-09	中文

Other Technical Documents

Title		Type	Date
	Clock Conditioner Owner's Manual	Design Guide	2006-11-10

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
LMK04031BISQ/NOPB RoHS Status	LLP	Full production Lead Time: 6 weeks	Distributor Region Qty DIGI-KEY Worldwide 0	$14.50 each at 1K+ pcs	reel of 1000
LMK04031BISQE/NOPB RoHS Status	LLP	Full production Lead Time: 6 weeks	Distributor Region Qty ARROW Worldwide 250 DIGI-KEY Worldwide 494 FARNELL Europe and Asia 54 MOUSER Worldwide 250 NEWARK Americas 54 TAYLOR Americas 250	$14.50 each at 1K+ pcs	reel of 250
LMK04031BISQX/NOPB RoHS Status	LLP	Full production Lead Time: 6 weeks	Distributor Region Qty CEAC Asia Pacific 37500 DIGI-KEY Worldwide 0	$14.50 each at 1K+ pcs	reel of 2500

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for LMK04031.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for LMK04031 is located at RoHS Status.

Part Number(s) (NSID)	Description	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
LMK04031BEVAL/NOPB	Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.5 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)	Full production Lead Free (RoHS)	Distributor Region Qty DIGI-KEY Worldwide 0 MOUSER Worldwide 2	$320.00 each	1
Description: The LMK04031 is a precision low noise programmable jitter cleaner, clock multiplier, and distribution device. The LMK04031, with two internal PLLs and an extremely high performance internal LC voltage controlled oscillator (VCO), can be combined with a low cost VCXO module or an external crystal and varactor diode to achieve ultra low jitter performance over all bandwidths. The LMK04031 has redundant reference clock inputs with loss of signal detection, featuring automatic revertive, automatic non-revertive, or manual selection of the reference clock. The LMK04031 is ideal for clocking high speed high resolution ADCs, DACs, local oscillators and FPGAs with its wide range of low phase noise output selections. The LMK04031 is particularly well suited for all the clocking needs of remote transceivers, high performance instruments and other applications that demand ultra low jitter and phase noise using local clock sources. Features: Integrated VCO for flexible low noise frequency multiplication Cascaded, integrated Integer-N PLLs. PLL2 normalized phase noise contribution is -224 dBc/Hz PLL1 supports up to 40 MHz phase detector rate. PLL2 supports up to 100 MHz phase detector rate Dual redundant reference clock inputs with loss of signal (LOS) detection and optional automatic switching after LOS is detected Typical root-mean-square (RMS) jitter performance at the VCO output is less than 200 fs (integrated from 100 Hz to 20 MHz) LVPECL, 2VPECL, LVDS, and LVCMOS outputs Five dedicated divider and delay channels Default Output Clock at startup, or after system reset, (Channel 2) to support application system configuration Pin compatible family of clocking devices 3.15 V to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Contents: Evaluation Board PC Interface Cable (uWire) Evaluation Board Instructions (PCB Rev. 2) Evaluation Board Instructions (PCB Rev. 3) Evaluation Board Software and Reference Tools http://www.national.com/analog/timing/codeloader Codeloader software Codeloader operating instructions National clock Design Tool

National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C1) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/en/packaging/greennopb.html. Lead free products are RoHS compliant.

Lead Free product status is available through the search tool located here

Part Number(s) (NSID)	Weight (milligrams)	Type	Pins	MSL Rating	Peak Reflow	RoHS Status	CAD Symbols	Models	Package Marking Format
LMK04031BISQ/NOPB	123.191	LLP	48	3	260	Detail	Download	ibis file	NS UZXYTTE# K04031BI
LMK04031BISQE/NOPB	123.191	LLP	48	3	260	Detail	Download	ibis file	NS UZXYTTE# K04031BI
LMK04031BISQX/NOPB	123.191	LLP	48	3	260	Detail	Download	ibis file	NS UZXYTTE# K04031BI

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for LMK04031.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for LMK04031 is located at RoHS Status.

Design Tools

Title	Size	Date
Design and Simulation Software & CodeLoader Programming Software
Powerwise Design University: Clock and Timing Webinar #1 - Clock Jitter Cleaners

CAD Symbols and Models Download LMK04031 CAD Symbols

Models ibis file

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMK04031BISQ	BICMOS8B+	0	3632	0	0	2762292	2	783807897
LMK04031BISQE	BICMOS8B+	0	3632	0	0	2762292	2	783807897
LMK04031BISQX	BICMOS8B+	0	3632	0	0	2762292	2	783807897

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for LMK04031.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for LMK04031 is located at RoHS Status.

Clock Design Tool - Getting Started Loading video... Clock Design Tool - Device Simulation Loading video... Clock Design Tool - Loop Filter Design Loading video... ADC16V130 16-bit, 130 MSPS Reference Subsystem Overview Loading video...

Clock Design Tool - Getting Started Date: 2010-03-22 Length: 0:11:48 Clock Design Tool - Device Simulation Date: 2010-03-22 Length: 0:08:52 Clock Design Tool - Loop Filter Design Date: 2010-03-22 Length: 0:05:31 ADC16V130 16-bit, 130 MSPS Reference Subsystem Overview Date: 2009-06-26 Length: 0:04:54