Features • Integrated VCO with very low phase noise floor • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz • VCO divider values of 2 to 8 (all divides) • Bypassable with VCO Mux when not in 0-delay mode • Channel divider values of 1, 2 to 510 (even divides) • LVDS and LVPECL clock outputs • Partially integrated loop filter • Dedicated divider and delay blocks on each clock output • 0-delay outputs • Internal or external feedback of output clock • Delay blocks on N and R phase detector inputs for lead/lag global skew adjust • Pin compatible family of clocking devices • 3.15 to 3.45 V operation • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) • 200 fs RMS Clock generator performance (10 Hz to 20 MHz) with a clean input clock Description The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family.

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Typical Application *click for larger image Apps Diagram	Block Diagram click for larger image Functional Block Diagram

Datasheet

Title		Size	Date	Other Language
	LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO	786 Kbytes	20-Aug-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1821: Application Note 1821 CPRI Repeater System	1497 Kbytes	15-May-08

More Application Notes

Title		Size	Date	Other Language
	AN-1865: Application Note 1865 Frequency Synthesis and Planning for PLL Architectures	151 Kbytes	6-Feb-09

Design Tools

Title	Size	Date
Clock Design Tool and Other Software for LMK Clock Conditioners
Evaluation Board Instruction	1658 Kbytes	23-Sep-2009

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMK03200ISQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
LMK03200ISQE	BICMOS8B+	0	1152	0	0	743900	5	211083656
LMK03200ISQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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