Features • 20 fs additive jitter • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz • Clock output frequency range of 1 to 800 MHz • 3 LVDS and 5 LVPECL clock outputs • Dedicated divider and delay blocks on each clock output • Pin compatible family of clocking devices • 3.15 to 3.45 V operation • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Description The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.

Also Recommended LMK01000 1.6 GHz Low-Noise Clock Distributor (LVPECL/LVDS Outputs) LMK02002▲ Clock Jitter Cleaner With External VCXO (LVPECL Outputs) LMK01010 1.6 GHz Low-Noise Clock Distributor (LVDS Outputs) LMK01020 1.6 GHz Low-Noise Clock Distributor (LVPECL Outputs) LMK03002C Clock Jitter Cleaner With Integrated 1.7 GHz VCO (LVPECL Outputs) Typical Application MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image Typical Application	Block Diagram *click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	LMK02000 Precision Clock Conditioner with Integrated PLL	453 Kbytes	4-Sep-07	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1821: Application Note 1821 CPRI Repeater System	1497 Kbytes	15-May-08
	AN-1734: Application Note 1734 Using the LMK03000C to Clean Recovered Clocks	188 Kbytes	2-May-08	中文
	AN-1865: Application Note 1865 Frequency Synthesis and Planning for PLL Architectures	151 Kbytes	6-Feb-09

More Application Notes

Title		Size	Date	Other Language
	AN-1602: Application Note 1602 LMH7322 Dual Comparator Evaluation Board	1838 Kbytes	30-Mar-07

Design Tools

Title	Size	Date
More design resources for the LMK clock conditoners
Clock Design Tool and Other Software for LMK Clock Conditioners

Reference Design

RD-147 - Low IF Receiver Reference Design Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMK02000ISQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
LMK02000ISQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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