Korean Chinese Traditional Chinese Simplified Japanese
 Home | About Us | Investors | Press Room | Private Sites


 
  LMK01020 - 1.6 GHz High Performance Clock Buffer, Divider, and Distributor from the PowerWise® Family

Datasheet Packaging Samples & Pricing Design Tools Knowledge Base

Features
 
•30 fs additive jitter (100 Hz to 20 MHz)
•Dual clock inputs
•Programmable output channels (0 to 1600 MHz)
 
•LMK01000: 3 LVDS outputs (CLKout0 - CLKout2) + 5 LVPECL outputs (CLKout3 - CLKout7)
•LMK01010: 8 LVDS outputs
•LMK01020: 8 LVPECL outputs
•Channel divider values of 1, 2 to 510 (even divides)
•Programmable output skew control
•External synchronization
•Pin compatible family of clocking devices
•3.15 to 3.45 V operation
•Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

General Description

The LMK01000/ LMK01010/ LMK01020 family provides an easy way to divide and distribute high performance clock signals throughout the system. More...

  Typical Application
*click for larger image

System Diagram

Parametric Table     expand
Parametric Table    collapse
Clock Output Freq Range 1 - 1600 MHz
Additive RMS Jitter 30 fs
LVDS Outputs 0
LVPECL Outputs 8
Min Supply Voltage 3.15 Volt
Max Supply Voltage 3.45 Volt
Temperature Min -40 deg C
Temperature Max 85 deg C
Clock Output Freq Range 1 - 1600 MHz
Additive RMS Jitter 30 fs
LVDS Outputs 0
LVPECL Outputs 8
Min Supply Voltage 3.15 Volt
Max Supply Voltage 3.45 Volt
Temperature Min -40 deg C
Temperature Max 85 deg C
RMS Jitter 0.03 ps
PowerWise Yes
View Using Catalog


Typical Performance

*click for larger image

LVPECL Output Noise Floor
  Also Recommended
LMK01000Distribution Only, 30fs Additive RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK01010Distribution Only, 30fs Additive RMS Jitter, 8 LVDS Outputs
LMK02000Integrated PLL Only, 0.2ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK02002Integrated PLL Only, 0.2ps RMS Jitter, 4 LVPECL Outputs
LMK03000VCO Range: 1185-1296 MHz, 0.8ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03000CVCO Range: 1185-1296 MHz, 0.4ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03000DVCO Range: 1185-1296 MHz, 1.2ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03001VCO Range: 1470-1570 MHz, 0.8ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03001CVCO Range: 1470-1570 MHz, 0.4ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03001DVCO Range: 1470-1570 MHz, 1.2ps RMS Jitter, 5 LVPECL + 3 LVDS Outputs
LMK03002VCO Range: 1566-1724 MHz, 0.8ps RMS Jitter, 4 LVPECL Outputs
LMK03002CVCO Range: 1566-1724 MHz, 0.4ps RMS Jitter, 4 LVPECL Outputs

Additional Resources

Design Tools (see below)


Block Diagram

*click for larger image

Functional Block Diagram

Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to View Online Click link below to Download Click link below to Receive via Email
LMK01000 / LMK01010 / LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor 437 Kbytes 6-Mar-08 View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
LMK01020ISQELLP48NOPB3260RoHS N/A Full production N/A
Samples500+$8.11reel
of
250		NS
UZXYTT
K01020 I
6 weeksN/A
LMK01020ISQLLP48NOPB3260RoHS N/A Full production N/A
Samples1K+$7.25reel
of
1000		NS
UZXYTT
K01020 I
6 weeksN/A
LMK01020ISQXLLP48NOPB3260RoHS N/A Full production N/A
 1K+$7.25reel
of
2500		NS
UZXYTT
K01020 I
20 weeksN/A

General Description

The LMK01000/ LMK01010/ LMK01020 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

The LMK01000/ LMK01010/ LMK01020 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

Design Tools

TitleSize in Kbytes Date Click link below to View Online Click link below to Download Click link below to Receive via Email
More design resources for the LMK clock conditoners 19 Kbytes 21-Apr-2008 View    

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 11-May-2008]