Features
30 fs additive jitter (100 Hz to 20 MHz)
Dual clock inputs
Programmable output channels (0 to 1600 MHz)
External synchronization
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
| Device
|
LVDS
Outputs
|
LVPECL
Outputs
|
| LMK01000
|
3
|
5
|
| LMK01010
|
8
|
0
|
| LMK01020
|
0
|
8
|
General Description
The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. More...
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Typical Application
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System Diagram
Parametric Table
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Parametric Table
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Typical Performance
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LVPECL Output Noise Floor
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Also Recommended
| LMK02000 | Clock Jitter Cleaner With External VCXO (LVPECL/LVDS Outputs) |
| LMK02002 | Clock Jitter Cleaner With External VCXO (LVPECL Outputs) |
| LMK03000C | Clock Jitter Cleaner With Integrated 1.2 GHz VCO (LVPECL/LVDS Outputs) |
| LMK03001C | Clock Jitter Cleaner With Integrated 1.5 GHz VCO (LVPECL/LVDS Outputs) |
| LMK03002C | Clock Jitter Cleaner With Integrated 1.7 GHz VCO (LVPECL Outputs) |
| LMK03033C | Clock Jitter Cleaner With Integrated 2.0 GHz VCO (LVPECL/LVDS Outputs) |
| LMK04031B | Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.5 GHz VCO (LVPECL/LVDS/LVCMOS Outputs) |
| LMK04033B | Clock Jitter Cleaner With Cascaded PLLs And Integrated 2.0 GHz VCO (LVPECL/LVDS/LVCMOS Outputs) |
| LMK04000B | Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.2 GHz VCO (LVPECL/LVCMOS Outputs) |

Additional Resources
Online Seminars
Design Tools (see below)

Block Diagram
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Functional Block Diagram
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