Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability:
SD clock: 27 MHz or 67.5 MHz
HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz
Low-jitter output clocks may be directly connected to an FPGA serializer to meet SMPTE SDI jitter specifications
Top of Frame (TOF) pulse with programmable output format timing and Hi-Z capability
Two reference ports (A and B) with H and V sync inputs
Supports cross-locking of input and output timing
External loop filter allows control of loop bandwidth, jitter transfer, and lock time characteristics
Free run or Holdover operation on loss of reference
User-defined free run control voltage input
I
2C interface and control registers
3.3V and 2.5V supplies
Description
The LMH1982 is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and
standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and
deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's
phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference
ports. The input reference can have analog timing from National's LMH1981 multi-format video sync separator or digital timing
from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device
can default to free run operation where the output timing accuracy will be determined by the external bias on the free run
control voltage input.
The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal
oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop
filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output
jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-pin LLP package and provides low total power consumption of about
250 mW (typical).
The LMH1982 evaluation board platform was designed by National Semiconductor to demonstrate the excellent clock jitter performance of the LMH1982 multi-rate video clock and timing generator in a genlock application with the LMH1981 multi-format video sync separator. The evaluation platform consists of the LMH1982 evaluation board and a USB interface board, and can be controlled from a PC using Nationals LMH1982 evaluation software.
The board provides input ports to apply analog or digital input reference signals and SMA output ports to transmit the LVDS SD and HD clocks. Headers and test points are provided to access other important I/O signals, such as the output Top of Frame (TOF) pulse timing generated by the LMH1982. The external VCXO and loop filter components are located on the top side of the board for easy modification and optimization of circuit performance. The on-board DIP switches can be used to control various input modes to the LMH1982, such as device reset and signal gating (tri-state) of the LMH1981 output syncs.
High-Performance SMPTE Video Clock Module for Xilinx ML571 Serial Digital Video Board
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National Semiconductor Enables the Xilinx Virtex 5 FPGA to Comply with SMPTE Jitter Requirements
The ML571-1982 CLK reference clock module features National Semiconductor`s highly-integrated multi-rate video clock generator. The LMH1982 can generate two simultaneous SD and HD output clocks genlocked to either the recovered H and V syncs from a Xilinx Virtex-5 LXT FPGA or from the outputs of an LMH1981 sync separator. Additionally, the LMH1982 provides an output Top of Frame timing pulse. In the event of a loss of reference, the device can be configured to default to either free run or holdover operation.
This reference design provides a proven video clocking solution for FPGAs that complies with stringent SDI jitter requirements, including the stringent SMPTE 424M standard for 3G-SDI. Integration, ease and flexibility of design, are demonstrated by the LMH1982 requiring a few additional components, and only one 27 MHz VCXO. An additional benefit of the LMH1982 is the programmable charge pump current control register for dynamic control of PLL bandwidth. A wide loop bandwidth can be programmed for faster PLL lock time or a narrow loop bandwidth can be programmed for maximum input attenuation.
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers
(CSP-9-111C1)
and Banned Substances and Materials of Interest Specification
(CSP-9-111S2)
for regulatory environmental compliance. Details may be found at:
www.national.com/en/packaging/greennopb.html.
Lead free products are RoHS compliant.
Lead Free product status is available through the search tool located
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Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
LMH1980
