RoHS Compliance Information	Size in Kbytes	Date
LMH1982 Multi-Rate Video Clock Generator with Genlock	735 Kbytes	29-Mar-09	Download

Part Number

Package

Factory Lead Time

Models

Samples & Electronic Orders

Budgetary Pricing

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Type

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Peak Reflow

RoHS Report

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$US each

LMH1982SQEEVAL

Evaluation Board for the LMH1982 Multi-Rate Video Clock Generator with LMH1981 HD/SD Video Sync Separator

Full production

N/A

1+

$325.00

1

-

N/A

N/A

ML571-1982CLK

High-Performance SMPTE Video Clock Module for Xilinx ML571 Serial Digital Video Board

Full production

N/A

1+

$299.00

1

-

N/A

N/A

LMH1982SQE

LLP

32

NOPB

1

260

RoHS

N/A

Full production

N/A

1K+

$16.50

reel of 250

NS UZXYTT L1982SQ

6 weeks

500

LMH1982SQ

LLP

32

NOPB

1

260

RoHS

N/A

Full production

N/A

1K+

$16.50

reel of 1000

NS UZXYTT L1982SQ

8 weeks

2000

LMH1982SQX

LLP

32

NOPB

1

260

RoHS

N/A

Full production

N/A

1K+

$16.50

reel of 4500

NS UZXYTT L1982SQ

8 weeks

N/A

General Description

The LMH1982 is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from National's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-pin LLP package and provides low total power consumption of about 250 mW (typical).

Reliability Metrics

Design Tools

Title	Size in Kbytes	Date
LMH1982 Evaluation Software User Guide	956 Kbytes	19-May-2008	View Online	Download
LMH1982 Software Setup	567 Kbytes	19-May-2008	View	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

Title	Size in Kbytes	Date
AN-1841: Application Note 1841 LMH1982 Evaluation Board User Guide	913 Kbytes	21-May-08	Download
AN-1841 (Chinese): Application Note 1841 LMH1982 Evaluation Board User Guide	599 Kbytes
AN-1893: Application Note 1893 Demonstrating SMPTE-Compliant SDI Output Jitter Using the LMH1982 and Virtex-5 GTP Transmitter	2197 Kbytes	3-Oct-08	Download
AN-1971: Application Note 1971 Triple Rate SDI IP FPGA Resource Utilization on the SDXILEVK/AES-EXP-SDI-G Reference Design	195 Kbytes	6-May-09	Download

More Application Notes

Title	Size in Kbytes	Date
AN-1681: Application Note 1681 Design Migration from the LM1881 to the LMH1980	143 Kbytes	2-Aug-07	Download
AN-1681 (Japanese): Application Note 1681 Design Migration from the LM1881 to the LMH1980	119 Kbytes
AN-1599: Application Note 1599 LMH1981 Evaluation Board Instruction Manual	503 Kbytes	11-Feb-09	Download
AN-1618: Application Note 1618 LMH1980 Evaluation Board Instruction Manual	674 Kbytes	19-Jul-07	Download
AN-1618 (Japanese): Application Note 1618 LMH1980 Evaluation Board Instruction Manual	412 Kbytes