Features • Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability: • SD clock: 27 MHz or 67.5 MHz • HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz • Low-jitter output clocks may be directly connected to an FPGA serializer to meet SMPTE SDI jitter specifications • Top of Frame (TOF) pulse with programmable output format timing and Hi-Z capability • Two reference ports (A and B) with H and V sync inputs • Supports cross-locking of input and output timing • External loop filter allows control of loop bandwidth, jitter transfer, and lock time characteristics • Free run or Holdover operation on loss of reference • User-defined free run control voltage input • I 2C interface and control registers • 3.3V and 2.5V supplies Description The LMH1982 is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems. The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from National's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input. The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications. The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-pin LLP package and provides low total power consumption of about 250 mW (typical). Applications • Video genlock and synchronization • FPGA SDI SerDes recovered clock generation • Triple rate 3G/HD/SD-SDI SerDes • Video capture, conversion, editing and distribution • Video displays and projectors • Broadcast and professional video equipment

Also Recommended LMH1981▲ Companion Multi-Format Video Sync Seperator MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram click for larger image
Typical Performance click for larger image

Datasheet

Title		Size	Date	Other Language
	LMH1982 Multi-Rate Video Clock Generator with Genlock	735 Kbytes	29-Mar-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1841: Application Note 1841 LMH1982 Evaluation Board User Guide	913 Kbytes	21-May-08	中文
	AN-1893: Application Note 1893 Demonstrating SMPTE-Compliant SDI Output Jitter Using the LMH1982 and Virtex-5 GTP Transmitter	2197 Kbytes	3-Oct-08
	AN-1971: Application Note 1971 Triple Rate SDI IP FPGA Resource Utilization on the SDXILEVK/AES-EXP-SDI-G Reference Design	195 Kbytes	6-May-09

More Application Notes

Title		Size	Date	Other Language
	AN-1681: Application Note 1681 Design Migration from the LM1881 to the LMH1980	143 Kbytes	2-Aug-07	日本語
	AN-1599: Application Note 1599 LMH1981 Evaluation Board Instruction Manual	503 Kbytes	11-Feb-09	日本語
	AN-1618: Application Note 1618 LMH1980 Evaluation Board Instruction Manual	674 Kbytes	19-Jul-07	日本語

Design Tools

Title	Size	Date
LMH1982 Evaluation Software User Guide	956 Kbytes	19-May-2008
LMH1982 Software Setup	567 Kbytes	19-May-2008

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMH1982SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
LMH1982SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656
LMH1982SQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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