Features * Patent applications made or pending. • SDTV/HDTV serial digital video standard compliant • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps serial video data rates with auto-detection • LSB de-dithering option • Uses low-cost 27MHz crystal or clock oscillator reference • Fast VCO lock time: < 500 µs at 1.485 Gbps • Built-in self-test (BIST) and video test pattern generator (TPG)* • Automatic EDH/CRC word and flag processing • Ancillary Data FIFO with extensive packet handling options • Adjustable, 4-deep parallel output video data FIFO • Flexible control and configuration I/O port • LVCMOS compatible control inputs and clock and data outputs • LVDS and ECL-compatible, differential, serial inputs • 3.3V I/O power supply and 2.5V logic power supply operation • Low power: typically 850mW • 64-pin TQFP package • Commercial temperature range 0°C to +70°C Description The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance. The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port. The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031. The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP. Applications • SDTV/HDTV serial-to-parallel digital video interfaces for: • Video editing equipment • VTRs • Standards converters • Digital video routers and switchers • Digital video processing and editing equipment • Video test pattern generators and digital video test equipment • Video signal generators

Also Recommended LMH0002▲ HD/SD Serial Digital Cable Driver LMH0030▲ HD/SD Digital Video Serializer W/ FIFOs And Integrated Cable Driver LMH0034▲ HD/SD Adaptive Cable Equalizer MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs	779 Kbytes	24-Jan-06

Featured Application Notes

Title		Size	Date	Other Language
	AN-1320: Application Note 1320 Enhancing LMH0031 Jitter Performance With Easy-To-Use VCXOs	446 Kbytes	3-Aug-06	中文
	AN-1336: Application Note 1336 CLC030 or CLC031 Control Port Bussed Operation	474 Kbytes	31-Jul-06	中文
	AN-1334: Application Note 1334 The LMH0030 in Segmented Frames Applications	451 Kbytes	1-Aug-06	中文

More Application Notes

Title		Size	Date	Other Language
	AN-2002: Application Note 2002 Replacing the CLC014 Adaptive Cable Equalizer with the LMH0074	158 Kbytes	22-Sep-09
	AN-2003: Application Note 2003 Replacing the CLC012 Adaptive Cable Equalizer with the LMH0074	160 Kbytes	6-Oct-09
	AN-1372: Application Note 1372 LMH0034 PCB Layout Techniques	908 Kbytes	31-Jul-06	日本語 中文

Design Tools

Title	Size	Date
SMPTE 292M/259M Digital Video Deserializer with Video and Ancillary Data FIFOs Evaluation Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMH0031VS	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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