Features * Patent applications made or pending. • SDTV/HDTV serial digital video standard compliant • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps SDV data rates with auto-detection • Low output jitter: 125ps max, 85ps typical • Low power: typically 430mW • No external serial data rate setting or VCO filtering components required* • Fast PLL lock time: < 150µs typical at 1.485 Gbps • Adjustable depth video FIFO for timing alignment • Built-in self-test (BIST) and video test pattern generator (TPG)* • Automatic EDH/CRC word and flag generation and insertion • On-chip ancillary data FIFO and insertion control circuitry • Flexible control and configuration I/O port • LVCMOS compatible data and control inputs and outputs • 75Ω ECL-compatible, differential, serial cable-driver outputs • 3.3V I/O power supply and 2.5V logic power supply operation • 64-pin TQFP package Description The LMH0030 SMPTE 292M/259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital video data conforming to SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high-definition, 20-bit wide component video standards. The LMH0030 operates at SMPTE 259M serial data rates of 270 Mbps, 360 Mbps, the SMPTE 344M serial data rate of 540 Mbps, and the SMPTE 292M serial data rates of 1483.5 and 1.485 Gbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components. The LMH0030 performs functions which include: parallel-to-serial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data, automatic video rate and format detection, ancillary data packet management and insertion, and serial data output driving. The LMH0030 has circuitry for automatic EDH/CRC character and flag generation and insertion per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). Optional LSB dithering is implemented which prevents pathological pattern generation. Unique to the LMH0030 are its video and ancillary data FIFOs. The video FIFO allows the video data to be delayed from 0 to 4 parallel data clock periods for video timing purposes. The ancillary data port and on-chip FIFO and control circuitry store and insert ancillary flags, data packets and checksums into the ancillary data space. The LMH0030 also has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with SD and HD component video test patterns: reference black, PLL and EQ pathologicals and color bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The color bar patterns feature optional bandwidth limiting coding in the chroma and luma transitions. The LMH0030 has a unique multi-function I/O port for immediate access to control and configuration settings. This port may be programmed to provide external access to control functions and indicators as inputs and outputs. The designer can thus customize the LMH0030 to fit the desired application. At power-up or after a reset command, the LMH0030 is auto-configured to a default operating condition. Separate power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise performance. The LMH0030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 430mW at 1.485 Gbps including two 75Ω AC-coupled and back-matched output loads. The device is packaged in a 64-pin TQFP. Applications • SDTV/HDTV parallel-to-serial digital video interfaces for: • Video cameras • VTRs • Telecines • Digital video routers and switchers • Digital video processing and editing equipment • Video test pattern generators and digital video test equipment • Video signal generators

Also Recommended LMH0002▲ HD/SD Serial Digital Cable Driver LMH0031▲ HD/SD Digital Video Deserializer & Descrambler LMH0034▲ HD/SD Adaptive Cable Equalizer MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver	602 Kbytes	10-Oct-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1334: Application Note 1334 The LMH0030 in Segmented Frames Applications	451 Kbytes	1-Aug-06	中文
	AN-1336: Application Note 1336 CLC030 or CLC031 Control Port Bussed Operation	474 Kbytes	31-Jul-06	中文
	AN-1320: Application Note 1320 Enhancing LMH0031 Jitter Performance With Easy-To-Use VCXOs	446 Kbytes	3-Aug-06	中文

More Application Notes

Title		Size	Date	Other Language
	AN-2002: Application Note 2002 Replacing the CLC014 Adaptive Cable Equalizer with the LMH0074	158 Kbytes	22-Sep-09
	AN-2003: Application Note 2003 Replacing the CLC012 Adaptive Cable Equalizer with the LMH0074	160 Kbytes	6-Oct-09
	AN-1372: Application Note 1372 LMH0034 PCB Layout Techniques	908 Kbytes	31-Jul-06	日本語 中文

Design Tools

Title	Size	Date
SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver Evaluation Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LMH0030VS	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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