Features
| | 3.3V Single Supply Operation |
| | CDS or S/H Processing |
| | 35 MHz Channel Rate |
| | Enhanced ESD Protection on Timing, Control and LVDS Pins |
| | Low Power CMOS Design |
| | 12 pin to 16 pin (selectable) LVDS serialized data output |
| | 4-Wire Serial interface |
| | 2 Channel Symmetrical Architecture |
| | Independent Gain and Offset Correction for each Channel |
| | Digital Black Level Calibration for each Channel |
| | Digital White Level Calibration for each Channel |
| | Programmable Input Clamp |
Key Specification
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Maximum Input Level
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1.2 Vp-p (CDS gain = 1.0)
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0.58 Vp-p (CDS gain = 2.0)
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Input Sample Rate
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5 to 35 MSPS - 6ch mode
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10 to 35 MSPS - 3ch mode
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PGA Gain Range
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1x to 10x (0 to 20 dB)
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CDS/SH Gain Settings
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1x or 2.1x
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Total Channel Gain
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1x to 21x (0 to 26 dB)
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PGA Gain Resolution
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8 bits - Analog
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ADC Resolution
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10 bits
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ADC Sampling Rate
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10 to 70 MSPS
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SNR
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68.5 dB (Gain = 1x)
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Offset DAC Range
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±111 mV or ±59.5 mV- FDAC
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|
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±281 mV - CDAC
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Offset DAC Resolution
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±10 bits - FDAC
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±4 bits - CDAC
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Supply voltage
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3.0V to 3.6V
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Power Dissipation
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1.02 W (typical)
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General Description
The LM98620 is a fully integrated, 10-Bit, 70 MSPS signal processing solution for high performance digital color copiers,
scanners, and other image processing applications. More...
| |
| Parameters | Values |
| Input Channels |
6 |
| ADC Sampling Rate |
70 MSPS |
| Channel Sampling Rate (MSPS) |
5 to 35 |
| ADC Resolution |
10 bits |
| Input Signal Polarity |
Both Pos, Neg |
| Input Sampler Type |
Both SH, CDS |
| Integrated Timing Generator |
No |
| Output Type |
LVDS |
| Input Voltage Swing (Max) |
1.2 Volt |
| INL (+/-) |
0.8 LSB |
| Noise Floor |
-68.5 dB |
| PGA Gain Resolution |
9 bits |
| PGA Gain (Min) |
0 dB |
| PGA Gain (Max) |
26 dB |
| DAC Offset Resolution (+/-) |
14 bits |
| DAC Offset Range (+/-) |
340 mV |
| Supply Voltage |
3.3 Volt |
| Power Dissipation |
1.02 Watt |
Block Diagram
click for larger image
System Block Diagram
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