Features
| • | 100% Software compatible with the CLC5903 |
| • | Pin compatible with the CLC5903 except for the analog input and reference section |
| • | 123 dB dynamic range with CLC5526 DVGA (200kHz) |
| • | On-chip precision reference |
| • | User Programmable AGC with enhanced Power Detector |
| • | Channel Filters include a Fourth Order CIC followed by 21-tap and 63-tap Symmetric FIRs |
| • | Flexible output formats |
| • | Serial and Parallel output ports |
| • | JTAG Boundary Scan |
| • | 8-bit Microprocessor Interface |
| • | 128 pin PQFP |
Description The LM97593 Dual ADC / Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated 12-bit analog-to-digital
converters (ADCs) and automatic gain control (AGC). The LM97593 further enhances National’s Diversity Receiver Chipset (DRCS)
by integrating a wide-bandwidth dual ADC core with the DDC. The complete DRCS includes one LM97593 Dual ADC / Digital Tuner
/ AGC and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). This system allows direct IF sampling of signals
up to 300MHz for enhanced receiver performance and reduced system costs. A block diagram for a DRCS-based narrowband communications
system is shown in
.
The LM97593 offers high dynamic range digital tuning and filtering based on hard-wired digital signal processing (DSP) technology.
Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering is performed
by a series of three filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter with a programmable decimation
ratio from 8 to 2048. Next there are two symmetric FIR filters, a 21-tap and a 63-tap, both with independent programmable
coefficients. The first FIR filter decimates the data by 2, the second FIR decimates by either 2 or 4. Channel filter bandwidth
at 52MSPS ranges from ±650kHz down to ±1.3kHz. At 65MSPS, the maximum bandwidth increases to ±812kHz.
The LM97593’s AGC controller monitors the ADC output and controls the ADC input signal level by adjusting the DVGA setting.
AGC threshold, deadband+hysteresis, and the loop time constant are user defined. Total dynamic range of greater than 123dB
full-scale signal to noise in a 200kHz bandwidth can be achieved with the Diversity Receiver Chipset.
Key Specification
|
Internal ADC Resolution
|
12 Bits
|
|
Sample Rate
|
65 MSPS
|
|
SNR (fIN = 250MHz, 11-bit, Nyquist)
|
62 dBFS (typ)
|
|
SNR (fIN = 250MHz, 200kHz)
|
83 dBFS (typ)
|
|
SFDR (fIN = 250MHz, 11-bit, Nyquist)
|
68 dBFS (typ)
|
|
Full Power Bandwidth
|
650 MHz (typ)
|
|
Power Consumption (65MSPS)
|
560 mW (typ)
|
Applications
| • | Cellular Basestations |
| • | GSM / GPRS / EDGE / GSM Phase 2 Receivers |
| • | Satellite Receivers |
| • | Wireless Local Loop Receivers |
| • | Digital Communications |
|
application circuit
|
LM97593
