Features • 18-bit i80 CPU Display Interface • Supports up to 640 x 480 VGA formats • Differential SLVS Interface • Dual displays supported • WRITE and READ operations supported • Robust Differential Physical Layer • 400mVpp differential signal swing • Internal 100 Ω Termination Resistor • Low Power Consumption • 5-bit CRC for data integrity • Level translation between host and display • Low Power sleep state • 3.3V Tolerant Master Clock Input regardless of VDDIO • Fast Start Up Time - 1k CLK cycles • 1.6V to 2.0V core / analog supply voltage • 1.6V to 3.0V I/O supply voltage range Description The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as common-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers. Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost. A low power sleep state entered when the PD* inputs are driven low.

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Datasheet

Title		Size	Date	Other Language
	LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave	1105 Kbytes	11-Sep-07

Featured Application Notes

Title		Size	Date	Other Language
	AN-71: Application Note 71 Micropower Circuits Using the LM4250 Programmable Op Amp	312 Kbytes	2-Oct-02

More Application Notes

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	AN-1932: Application Note 1932 LMP2021MAEVAL - Bridge Sensor Instrumentation Amplifier Evaluation Board User Guide	176 Kbytes	10-Dec-08

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LM4308GR	CMOS9T	0	2160	0	0	2397152	2	680198425
LM4308GRX	CMOS9T	0	2160	0	0	2397152	2	680198425
LM4308SQ	CMOS9T	0	2160	0	0	2397152	2	680198425
LM4308SQX	CMOS9T	0	2160	0	0	2397152	2	680198425

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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