Features • 24-bit RGB Interface support up to 640 x 480 VGA format • Optional 24 to 18-bit Dithering • Optional Look Up Table for independent color correction • MPL-1 Physical Layer • SPI Interface for Look Up Table control and loading • Low Power Consumption & Powerdown state • Level translation between host and display • Optional Auto Power Down on STOP PCLK • Frame Sequence bits auto resync upon data or clock error • 1.6V to 2.0V core / analog supply voltage • 1.6V to 3.0V I/O supply voltage range Description The LM2512A is a MPL Serializer (SER) that performs a 24-bit to 18-bit Dither operation and serialization of the video signals to Mobile Pixel link (MPL) levels on only 3 or 4 active signals. An optional Look Up Table (Three X 256 X 8 bit RAM) is also provided for independent color correction. 18-bit Bufferless or partial buffer displays from QVGA (320 x 240) up to VGA (640 x 480) pixels can utilize a 24-bit video source. The interconnect is reduced from 28 signals to only 3 or 4 active signals with the LM2512A and companion deserializer easing flex interconnect design, size constraints and cost. The LM2512A SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near or in the display module. When in Power_Down, the SER is put to sleep and draws less than 10μA. The link can also be powered down by stopping the PCLK (DES dependant) or by the PD* input pins. The LM2512A provides enhanced AC performance over the LM2512. It implements the physical layer of the MPL-1 and uses a single-ended current-mode transmission.

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Datasheet

Title		Size	Date	Other Language
	LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table	453 Kbytes	11-Sep-07

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Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LM2512ASM	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2512ASMX	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2512ASN	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2512ASNX	CMOS9T	0	2160	0	0	2397152	2	680198425

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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