Features • RGB Display Interface support up to 800 x 300 ½SVGA formats • MPL-Level 0 Physical Layer using two data and one clock signal • Low Power Consumption • Pinout mirroring enables straight through layout with minimal vias • Level translation between host and display • Auto Power Down on STOP PCLK • Link power down mode reduces quiescent power under < 10 µA • 1.74V to 2.0V core / analog supply voltage range • 1.74V to 3.0V I/O supply voltage range • -30C to 85C Operating temperature range Description The LM2506 device adapts RGB style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. The LM2506 supports one RGB display at up to 18-bit color depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz PCLK) is supported. A mode pin configures the device as a Serializer (SER) or Deserializer (DES) so the same chip can be used on both sides of the interface. The interconnect is reduced from 22 signals to only 3 active signals with the LM2506 chipset easing flex interconnect design, size constraints and cost. The LM2506 in SER mode resides beside an application, graphics or baseband processor and translates a parallel bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near the display module. When the Power_Down (PD*) input is asserted on the SER, the MDn and MC line drivers are powered down to save current. The DES can be controlled by a separate Power_Down input or via a signal from the SER (PDOUT*). The LM2506 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 µA IB current (Class 0).

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Datasheet

Title		Size	Date	Other Language
	LM2506 Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB Display Interface Serializer and Deserializer	855 Kbytes	7-Aug-06

Featured Application Notes

Title		Size	Date	Other Language
	AN-1861: Application Note 1861 LM25037 Evaluation Board	1088 Kbytes	18-Dec-08

More Application Notes

Title		Size	Date	Other Language
	AN-1947: Application Note 1947 LM25069 Evaluation Board	483 Kbytes	29-Jun-09	中文
	AN-1311: Application Note 1311 MPL PHY Layer Overview	151 Kbytes	19-Jan-04	中文
	AN-1946: Application Note 1946 LM25061 Evaluation Board	470 Kbytes	29-Jun-09	中文

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LM2506GR	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2506GRX	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2506SQ	CMOS9T	0	2160	0	0	2397152	2	680198425
LM2506SQX	CMOS9T	0	2160	0	0	2397152	2	680198425

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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