LM2502 - Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer

LM2502 - Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer from the PowerWise® Family

Datasheet	Packaging	Samples & Pricing	Reliability	Knowledge Base

Features

•	>300 Mbps Dual Link Raw Throughput
•	MPL Physical Layer (MPL-0)
•	Pin selectable Master / Slave mode
•	Frequency Reference Transport
•	Complete LVCMOS / MPL Translation
•	Interface Modes:
•	16-bit CPU, i80 or m68 style
•	RGB565 with glue logic
•	-30°C to 85°C Operating Range
•	Link power down mode reduces I_DDZ < 10 µA
•	Dual Display Support (CS1* & CS2*)
•	Via-less MPL interconnect feature
•	3.0V Supply Voltage (V_DD and V_DDA)
•	Interfaces to 1.7V to 3.3V Logic (V_DDIO)

General Description

The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. More...

Typical Application

click for larger image

Parameters Values

Function Master/Slave

Bits 8 or 16

Max PCLK Frequency 26 MHz

VDDP 2.9 to 3.3V

VDDI/O 1.8 to 3.3V

Read/Write Yes

Target Application Mobile Phone

Recommended Interface CPU

Selectable Edge Rate No

PowerWise Technology Mobile Pixel Link Bridge

External Filters Req'd No

I/O Levels MPL-1

Special Features Optional Clock Output

ESD 2 kV

Typical Performance

*click for larger image

Connection Diagram

*click for larger image

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer	1089 Kbytes	17-Jan-06	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

LM2502SM

UFBGA

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$1.45

reel
of
1000

ZXYTT
L2502

6 weeks

1000

LM2502SMX

UFBGA

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$1.45

reel
of
4500

ZXYTT
L2502

6 weeks

N/A

LM2502SQ

LLP

NOPB

260

RoHS

N/A

Preliminary

N/A

1K+

$1.45

reel
of
1000

NS
UZXYTT
L2502SQ

12 weeks

500

LM2502SQX

LLP

NOPB

260

RoHS

N/A

Preliminary

N/A

1K+

$1.45

reel
of
4500

NS
UZXYTT
L2502SQ

12 weeks

N/A

General Description

The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.

The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module.

Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface.

The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current.

The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) UFBGA and LLP packages.

Reliability Metrics

Part Number	Process	EFR Sample Size	LTA Device Hours	FITS	MTTF (Hours)
LM2502SM	CMOS7	18406	1089000	4	309006723
LM2502SMX	CMOS7	18406	1089000	4	309006723
LM2502SQ	CMOS7	18406	1089000	4	309006723
LM2502SQX	CMOS7	18406	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Application Notes

Title	Size in Kbytes	Date
AN-1311: Application Note 1311 MPL PHY Layer Overview	151 Kbytes	19-Jan-04	Download
AN-1311 (Chinese): Application Note 1311 MPL PHY Layer Overview	369 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 7-Nov-2009]