Features • >300 Mbps Dual Link Raw Throughput • MPL Physical Layer (MPL-0) • Pin selectable Master / Slave mode • Frequency Reference Transport • Complete LVCMOS / MPL Translation • Interface Modes: • 16-bit CPU, i80 or m68 style • RGB565 with glue logic • -30°C to 85°C Operating Range • Link power down mode reduces IDDZ < 10 µA • Dual Display Support (CS1* & CS2*) • Via-less MPL interconnect feature • 3.0V Supply Voltage (VDD and VDDA) • Interfaces to 1.7V to 3.3V Logic (VDDIO) Description The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost. The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module. Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface. The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current. The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) UFBGA and LLP packages.

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Typical Application click for larger image	Connection Diagram *click for larger image *click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer	1089 Kbytes	17-Jan-06

Featured Application Notes

Title		Size	Date	Other Language
	AN-1311: Application Note 1311 MPL PHY Layer Overview	151 Kbytes	19-Jan-04	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1431: Application Note 1431 LM25010 Evaluation Board	632 Kbytes	19-Dec-05

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
LM2502SM	CMOS7	0	18406	0	0	1089000	4	309006723
LM2502SMX	CMOS7	0	18406	0	0	1089000	4	309006723
LM2502SQ	CMOS7	0	18406	0	0	1089000	4	309006723
LM2502SQX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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