LF398A - Monolithic Sample and Hold Circuit [Obsolete]

	LF398A - Monolithic Sample and Hold Circuit [Obsolete]

Datasheet	Obsolete Parts	Knowledge Base

Features

Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from ±5V to ±18V supplies. An "A" version is available with tightened electrical specifications.

•	Operates from ±5V to ±18V supplies
•	Less than 10 µs acquisition time
•	TTL, PMOS, CMOS compatible logic input
•	0.5 mV typical hold step at C_h = 0.01 µF
•	Low input offset
•	0.002% gain accuracy
•	Low output noise in hold mode
•	Input characteristics do not change during hold mode
•	High supply rejection ratio in sample or hold
•	Wide bandwidth
•	Space qualified, JM38510

General Description

The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. More...

Typical Application

See Datasheet for Application Information

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits	520 Kbytes	23-Aug-00	View Online Download
LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits (Japanese)	532 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Obsolete Parts

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
LF398AH	LF198AH	NSC	12/03/2008

General Description

The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 10¹⁰Ohm allows high source impedances to be used without degrading accuracy.

P-channel junction FET's are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 µF hold capacitor. The JFET's have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages.

[Information as of 10-Oct-2008]