Features • 5 MHz–43 MHz embedded clock & DC-Balanced data transmission (21 total LVDS data bits plus 3 low speed LVCMOS data bits) • User adjustable pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable • Supports AC-coupling data transmission • 100Ω Integrated termination resistor at LVDS input • Power-down control • Available @SPEED BIST to DS90UR124 to validate link integrity • All LVCMOS inputs & control pins have internal pulldown • Schmitt trigger inputs on OS[2:0] to minimize metastable conditions. • Outputs Tri-Stated through DEN • On-chip filters for PLLs • Power supply range 3.3V ± 10% • Automotive temperature range −40°C to +105°C • Greater than 8kV ESD Tolerance • Meets ISO 10605 ESD and AEC-Q100 compliance Description The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins. The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

Also Recommended DS90UR124▲ Deserializer, 5-43 MHz, –40°C To +105°C, 10 M Drive Strenght MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image	Connection Diagram *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS99R421 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC-Balanced) Converter	1036 Kbytes	1-Sep-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1807: Application Note 1807 FPD-Link II Display SerDes Overview	106 Kbytes	4-Nov-09

More Application Notes

Title		Size	Date	Other Language
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

Design Tools

Title	Size	Date
Evaluation Kit for DS99R421 Serializer

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS99R421ISQ	CMOS7	0	18406	0	0	1089000	4	309006723
DS99R421ISQX	CMOS7	0	18406	0	0	1089000	4	309006723
DS99R421QSQ	CMOS7	0	18406	0	0	1089000	4	309006723
DS99R421QSQX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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