DS99R105 - 3-40MHz DC- Balanced 24-Bit LVDS Serializer

Datasheet	Packaging	Samples & Pricing	Eval. Boards	Reliability	Design Tools	Application Notes	Knowledge Base

Features

•	3 MHz–40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions
•	Capable to drive shielded twisted-pair cable
•	User selectable clock edge for parallel data on both Transmitter and Receiver
•	Internal DC Balancing encode/decode – Supports AC-coupling interface with no external coding required
•	Individual power-down controls for both Transmitter and Receiver
•	Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed
•	All codes RDL (random data lock) to support live-pluggable applications
•	LOCK output flag to ensure data integrity at Receiver side
•	Balanced T_SETUP/T_HOLD between RCLK and RDATA on Receiver side
•	PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects
•	All LVCMOS inputs and control pins have internal pulldown
•	On-chip filters for PLLs on Transmitter and Receiver
•	Integrated 100Ω input termination on Receiver
•	4 mA Receiver output drive
•	48-pin TQFP and 48-pin LLP packages
•	Pure CMOS .35 μm process
•	Power supply range 3.3V ± 10%
•	Temperature range 0°C to +70°C
•	8 kV HBM ESD tolerance

General Description

The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. More...

Typical Application

*click for larger image

Parameters Values

Function Serializer

Color Depth 18 bpp

Pixel Clock Max 40 MHz

Pixel Clock Min 3 MHz

Input Compatibility LVCMOS

Output Compatibility FPD-Link LVDS

Signal Conditioning Fixed Pre-Emphasis

Total Throughput 960 Mbps

Payload/Channel 960 Mbps

Reference Clock Req'd Deserializer No

Embedded Clock Yes

Parallel Bus Width 24 bits

Special Features Fixed Pre-Emphasis

ESD 8 kV

Supply Voltage 3.3 Volt

Temperature Min 0 deg C

Temperature Max 70 deg C

PowerWise No

Automotive No

Communications No

Sensing & Imaging Yes

DisplayType LCD

Also Recommended

DS90C241▲	Serializer & DS90C124 Deserializer Chipset, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
DS90UR241▲	Serializer & DS90UR124 Deserializer Chipset, 5-43 MHz, –40°C To +105°C, 10 Meter Drive Strength
DS99R101▲	Serializer & DS99R102 Deserializer Chipset, 3-40 MHz, 0°C To +70°C, 2 Meter Drive Strength
DS99R103▲	Serializer & DS99R104 Deserializer Chipset, 3-40 MHz, -40°C To +85°C, 5 Meter Drive Strength
DS99R106▲	Deserializer, 3-40 MHz, 0°C To +70°C, 10 Meter Drive Strength (FOR COMPLETE CHIPSET)

Additional Resources

Design Tools

Application Notes

Connection Diagram

*click for larger image

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer	928 Kbytes	15-Oct-07	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

SERDES05-40USB

Evaluation Kit for DS99R105/DS99R106 FPD-Link II Serializer and Deserializer Chipset

Full production

N/A

$199.00

N/A

DS99R105SQ

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.25

reel
of
2500

NS
UZXYTTE#
DS99R105

6 weeks

500

DS99R105SQX

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.25

reel
of
2500

NS
UZXYTTE#
DS99R105

6 weeks

N/A

DS99R105VS

TQFP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.25

tray
of
250

NSUZXYTT
DS99R105
VS

8 weeks

DS99R105VSX

TQFP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.25

reel
of
1000

NSUZXYTT
DS99R105
VS

8 weeks

N/A

General Description

The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

Reliability Metrics

Part Number	Process	EFR Sample Size	LTA Device Hours	FITS	MTTF (Hours)
DS99R105SQ	CMOS7	18406	1089000	4	309006723
DS99R105SQX	CMOS7	18406	1089000	4	309006723
DS99R105VS	CMOS7	18406	1089000	4	309006723
DS99R105VSX	CMOS7	18406	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
LVDS Owner's Manual - 4th Edition			View
Evaluation Kit for DS99R105/DS99R106 FPD-Link II Serializer and Deserializer Chipset			View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

Title	Size in Kbytes	Date
AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 7-Nov-2009]