3 MHz–40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions
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Capable to drive shielded twisted-pair cable
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User selectable clock edge for parallel data on both Transmitter and Receiver
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Internal DC Balancing encode/decode – Supports AC-coupling interface with no external coding required
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Individual power-down controls for both Transmitter and Receiver
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Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed
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All codes RDL (random data lock) to support live-pluggable applications
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LOCK output flag to ensure data integrity at Receiver side
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Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side
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PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects
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All LVCMOS inputs and control pins have internal pulldown
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On-chip filters for PLLs on Transmitter and Receiver
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Integrated 100Ω input termination on Receiver
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4 mA Receiver output drive
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48-pin TQFP and 48-pin LLP packages
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Pure CMOS .35 μm process
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Power supply range 3.3V ± 10%
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Temperature range 0°C to +70°C
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8 kV HBM ESD tolerance
Description
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating
the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce
PCB layers, cable width, and connector size and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment
for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating
frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced
encoding/decoding is used to support AC-Coupled interconnects.
The SERDES05-40USB is an evaluation kit designed to demonstrate performance and capabilities of the DS99R105 and DS99R106 FPD-Link II Serializer/Deserializer Chipset.
The DS99R105 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. The DS99R106 Deserializer board accepts the FPD-Link II LVDS serialized data stream and converts the data back into parallel LVCMOS signals and clock. USB cable is provided as a generic medium for the high speed data link. Jumpers and switches on the boards can be configured for evaluation of chipset features.
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
DS99R105
DS90C241
