Features • Wide Operating Range Embedded Clock SER/DES • Up to 32-bit parallel LVCMOS data • 20 to 85 MHz parallel clock • Up to 2.72 Gbps application data paylod • Selectable Serial LVDS Bus Width • Dual Lane Mode (20 to 50 MHz) • Quad Lane Mode (40 to 85 MHz) • Simplified Clocking Architecture • No separate serial clock line • No reference clock required • Receiver locks to random data • On-chip Signal Conditioning for Robust Serial Connectivity • Transmit Pre-Emphasis • Data randomization • DC-balance encoding • Receive channel deskew • Supports up to 10m CAT-5 at 2.7 Gbps • Integrated LVDS Terminations • Built-in AT-SPEED BIST for end-to-end system testing • AC-coupled interconnect for isolation and fault protection • > 4KV HBM ESD protection • Space-saving 64-pin TQFP package • Full industrial temperature range : -40° to +85°C Description The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus. On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation. By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics. Applications • Industrial imaging (Machine-vision) and control • Security & Surveillance cameras and infrastructure • Medical imaging • Up to 30 bits per pixel, VGA to HD video transport and display

LV3241 Typ Connection Diag MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image LV3241 Typ Connection Diag	Block Diagram click for larger image Typ App Diagram
Typical Performance click for larger image Quad85MHz VODHIGH Typ Perf

Datasheet

Title		Size	Date	Other Language
	DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	1806 Kbytes	17-Sep-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1376: Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs	1758 Kbytes	2-May-05
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS92LV3241TVS	CMOS7	0	18406	0	0	1089000	4	309006723
DS92LV3241TVSX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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