Features • 15-66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps full duplex throughput) • Independent transmitter and receiver operation with separate clock, enable, and power down pins • Hot plug protection (power up high impedance) and synchronization (receiver locks to random data) • Wide ±5% reference clock frequency tolerance for easy system design using locally-generated clocks • Line and local loopback modes • Robust BLVDS serial transmission across backplanes and cables for low EMI • No external coding required • Internal PLL, no external PLL components required • Single +3.3V power supply • Low power: 90mA (typ) transmitter, 100mA (typ) at 66 MHz with PRBS-15 pattern • ±100 mV receiver input threshold • Loss of lock detection and reporting pin • Industrial -40 to +85°C temperature range • >2.0kV HBM ESD • Compact, standard 80-pin LQFP package Description The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18-bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

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Datasheet

Title		Size	Date	Other Language
	DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz	859 Kbytes	30-Jun-06	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1376: Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs	1758 Kbytes	2-May-05
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04

Design Tools

Title	Size	Date
18-bit SerDes Design Guide	2886 Kbytes	29-Mar-2007
18-Bit Bus LVDS SERDES Evaluation Board 15-66 MHz

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS92LV18TVV	CMOS8	1	13140	55	0	1615500	3	458102536
DS92LV18TVVX	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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