DS92LV18 - 18-Bit Bus LVDS Serializer/Deserializer

DS92LV18 - 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Datasheet	Packaging	Samples & Pricing	Eval. Boards	Reliability	Design Tools	Models	Application Notes	Knowledge Base

Features

•	15-66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps full duplex throughput)
•	Independent transmitter and receiver operation with separate clock, enable, and power down pins
•	Hot plug protection (power up high impedance) and synchronization (receiver locks to random data)
•	Wide ±5% reference clock frequency tolerance for easy system design using locally-generated clocks
•	Line and local loopback modes
•	Robust BLVDS serial transmission across backplanes and cables for low EMI
•	No external coding required
•	Internal PLL, no external PLL components required
•	Single +3.3V power supply
•	Low power: 90mA (typ) transmitter, 100mA (typ) at 66 MHz with PRBS-15 pattern
•	±100 mV receiver input threshold
•	Loss of lock detection and reporting pin
•	Industrial -40 to +85°C temperature range
•	>2.0kV HBM ESD
•	Compact, standard 80-pin LQFP package

General Description

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18-bit parallel bus into a BLVDS serial stream with embedded clock information. More...

Parameters Values

Function SerDes

Total Throughput 2376 Mbps

Payload/Channel 1188 Mbps

Clock Min 15 MHz

Clock Max 66 MHz

Input Compatibility LVTTL, BLVDS

Output Compatibility LVDS/BLVDS, LVTTL

Start/Stop Bit Yes

Power Consumption_ 726 mW

SupplyVoltage 3.3 Volt

Eval Kit LVDS-18B-EVK

ESD 2 kV

Temperature Min -40 deg C

Temperature Max 85 deg C

Compression Ratio 18:1

Parallel Bus Width 18 bits

Number Transmitters 1

Number Receivers 1

Communications Yes

Sensing & Imaging Yes

Typical Performance

*click for larger image

Additional Resources

Online Seminars

Boosting FPGA and CPLD Interface Performance for off-board Data Transmission

Design Tools

Application Notes

Block Diagram

click for larger image

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz	859 Kbytes	30-Jun-06	Download
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz (Japanese)	751 Kbytes

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Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

LVDS-18B-EVK

18-Bit Bus LVDS SERDES Evaluation Board 15-66 MHz

Preliminary

N/A

$399.00

N/A

DS92LV18TVV

LQFP

NOPB
STD

3
3

260
260

RoHS

Download

Full production

ds92lv18tvv.ibs

1K+

$8.10

tray
of
119

NSUZXYTTE#
DS92LV18TVV
BBBBB

6 weeks

500

DS92LV18TVVX

LQFP

NOPB

260

RoHS

Download

Full production

N/A

1K+

$8.10

reel
of
1000

NSUZXYTTE#
DS92LV18TVV
BBBBB

12 weeks

N/A

General Description

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18-bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS92LV18TVV	CMOS8	1	13140	55	0	1615500	3	458102536
DS92LV18TVVX	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
18-bit SerDes Design Guide	2886 Kbytes	29-Mar-2007	View Online	Download
18-Bit Bus LVDS SERDES Evaluation Board 15-66 MHz			View

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Application Notes

Title	Size in Kbytes	Date
AN-1376: Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs	1758 Kbytes	2-May-05	Download
AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	Download

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More Application Notes

Title	Size in Kbytes	Date
AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04	Download

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[Information as of 8-Nov-2009]