DS92LV16 - 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

Datasheet Packaging Samples & Pricing Eval. Boards Reliability Design Tools Models Knowledge Base

Features
•25-80 MHz 16:1/1:16 serializer/deserializer (2.56Gbps full duplex throughput)
•Independent transmitter and receiver operation with separate clock, enable, power down pins
•Hot plug protection (power up high impedance) and synchronization (receiver locks to random data)
•Wide +/-5% reference clock frequency tolerance for easy system design using locally-generated clocks
•Line and local loopback modes
•Robust BLVDS serial transmission across backplanes and cables for low EMI
•No external coding required
•Internal PLL, no external PLL components required
•Single +3.3V power supply
•Low power: 104mA (typ) transmitter, 119mA (typ) receiver at 80MHz
•±100mV receiver input threshold
•Loss of lock detection and reporting pin
•Industrial -40 to +85°C temperature range
•>2.5kV HBM ESD
•Compact, standard 80-pin PQFP package

General Description

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16-bit parallel bus into a BLVDS serial stream with embedded clock information. More...


  Typical Application
See Datasheet for Application Information

Parametric Table     expand
Parametric Table    collapse
Function SerDes
Total Throughput 2560 Mbps
Payload/Channel 1280 Mbps
Clock Min 25 MHz
Clock Max 80 MHz
Compression Ratio 16:1
Function SerDes
Total Throughput 2560 Mbps
Payload/Channel 1280 Mbps
Clock Min 25 MHz
Clock Max 80 MHz
Input Compatibility LVTTL, LVDS/BLVDS
Output Compatibility LVDS/BLVDS, LVTTL
Start/Stop Bit Yes
Power Consumption_ 743 mW
SupplyVoltage 3.3 Volt
Eval Kit BLVDS16EVK
ESD 2.5 kV
Temperature Min -40 deg C
Temperature Max 85 deg C
Compression Ratio 16:1
Number Transmitters 1
Number Receivers 1
Communications Yes
Sensing & Imaging Yes
Parallel Bus Width 16 bits
View Using Catalog


Typical Performance

*click for larger image


  Also Recommended
DS92LV1815-66 MHz 18-bit SerDes

Additional Resources

Online Seminars Design Tools (see below)


Block Diagram

*click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz 397 Kbytes 20-Feb-02 Download
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz (Japanese)
 256 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
BLVDS16EVK16-bit Bus LVDS SERDES Evaluation BoardPreliminaryN/A
 
Buy Now 		1+$399.001-
N/AN/A
DS92LV16TVHGLQFP80STD
NOPB		3
3		260
260		RoHS Download Full production
ds92lv16tvhg.ibs		 
Buy Now 		1K+$7.99tray
of
119		NSUZXYTT
DS92LV16TVHG
BBBBB
12 weeks500
DS92LV16TVHGXLQFP80STD
NOPB		3
3		260
260		RoHS Download Full productionN/A
 
Buy Now 		1K+$7.99reel
of
1000		NSUZXYTT
DS92LV16TVHG
BBBBB
16 weeks2000

General Description

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16-bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS92LV16TVHGCMOS811219583014105003400233226
DS92LV16TVHGXCMOS811219583014105003400233226

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Design Tools

TitleSize in Kbytes Date Click link below to Download    
DS92LV16 Design Guide 3082 Kbytes 29-Mar-2007 View Online Download  
16-bit Bus LVDS SERDES Evaluation Board     View    

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Application Notes

TitleSize in Kbytes Date Click link below to Download
AN-1376: Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs 1758 Kbytes 2-May-05 Download
AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask 339 Kbytes 2-May-04 Download
AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES 360 Kbytes 2-Mar-09 Download

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[Information as of 5-Jul-2009]