Features • Clock recovery without SYNC patterns-random lock • Guaranteed transition every data transfer cycle • Chipset (Tx + Rx) power consumption < 300mW (typ) @ 40MHz • Single differential pair eliminates multi-channel skew • 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) • 10-bit parallel interface for 1 byte data plus 2 control bits or UTOPIA I Interface • Synchronization mode and LOCK indicator • Flow-through pinout for easy PCB layout • High impedance on receiver inputs when power is off • Programmable edge trigger on clock • Footprint compatible with DS92LV1210 • Small 28-lead SSOP package-MSA Description The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212A receives a Bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock. The reduced cable, PCB trace count and connector size saves cost and makes PCB layout easier. Clock-to-data and data-to-data skews are eliminated since one input receives both clock and data bits serially. The powerdown pin is used to save power by reducing the supply current when the device is not in use. The Deserializer will establish lock to a synchronization pattern within specified lock times but it can also lock to a data stream without SYNC patterns.

Also Recommended DS92LV1224▲ 40 - 66 Mhz Operating Frequency Range SCAN921226▲ Increased Operating Range To 80 Mhz DS92LV1260▲ Integrates Six 1:10 Deserializer Channels Into A Single Chip SCAN921224▲ DS92LV1224 With JTAG Boundary SCAN And At-Speed LVDS Test MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	366 Kbytes	17-Nov-00	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04
	AN-1238: Application Note 1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices	64 Kbytes	14-May-04
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文
	AN-1238: Application Note 1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices	64 Kbytes	14-May-04

Design Tools

Title	Size	Date
10-Bit Bus LVDS Serializer / Deserializer Evaluation Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS92LV1212AMSA	CMOS8	1	13140	55	0	1615500	3	458102536
DS92LV1212AMSAX	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.