Features • Guaranteed transition every data transfer cycle • Single differential pair eliminates multi-channel skew • Flow-through pinout for easy PCB layout • 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) • 10-bit parallel interface for 1 byte data plus 2 control bits • Programmable edge trigger on clock • Bus LVDS serial output rated for 27 load • Small 28-lead SSOP package-MSA Description The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1021A can transmit data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits both clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when the device is not being used. Upon power up of the Serializer, you can choose to activate synchronization mode or use one of National Semiconductor's Deserializers in the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1021A output pins into TRI-STATE® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.

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Datasheet

Title		Size	Date	Other Language
	DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer	209 Kbytes	29-Jan-03	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1238: Application Note 1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices	64 Kbytes	14-May-04

Design Tools

Title	Size	Date
10-Bit Bus LVDS Serializer / Deserializer Evaluation Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS92LV1021AMSA	CMOS8	1	13140	55	0	1615500	3	458102536
DS92LV1021AMSAX	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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