DS91M040 - 125 MHz Quad M-LVDS Transceiver

Datasheet Packaging Samples & Pricing Eval. Boards Design Tools Models Knowledge Base

Features
•DC - 125 MHz / 250 Mbps low jitter, low skew, low power operation
•Wide Input Common Mode Voltage Range allows up to ±1V of GND noise
•Conforms to TIA/EIA-899 M-LVDS Standard
•Pin selectable M-LVDS receiver type (1 or 2)
•Controlled transition times (2.0 ns typ) minimize reflections
•8 kV ESD on M-LVDS I/O pins protects adjoining components
•Flow-through pinout simplifies PCB layout
•Small 5 mm x 5 mm LLP-32 space saving package

General Description

The DS91M040 is a quad M-LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. More...


Applications


•Multidrop / Multipoint clock and data distribution
•High-Speed, Low Power, Short-Reach alternative to TIA/EIA-485/422
•Clock distribution in AdvancedTCA (ATCA) and
• MicroTCA (μTCA, uTCA) backplanes
  Typical Application
*click for larger image


Parametric Table     expand
Parametric Table    collapse
Temperature Min -40 deg C
Temperature Max 85 deg C
Temperature Min -40 deg C
Temperature Max 85 deg C
Function Transceiver
View Using Catalog


Typical Performance

*click for larger image


  Additional Resources
Design Tools (see below)


Block Diagram

*click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS91M040 125 MHz Quad M-LVDS Transceiver 400 Kbytes 15-Oct-08 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
DS91M040EVKDS91M040EVK DocumentationPreliminaryN/A
 
Buy Now 		1+$125.001-
N/AN/A
DS91M040TSQELLP32NOPB3260RoHS N/A Full production
ds91m040.ibs		 
Buy Now 		1K+$3.79reel
of
250		NS
UZXYTT
M040TS
6 weeksN/A
DS91M040TSQLLP32NOPB3260RoHS N/A Full production
ds91m040.ibs		Samples
Buy Now 		1K+$3.79reel
of
1000		NS
UZXYTT
M040TS
6 weeksN/A
DS91M040TSQXLLP32NOPB3260RoHS N/A Full production
ds91m040.ibs		 
Buy Now 		1K+$3.79reel
of
4500		NS
UZXYTT
M040TS
8 weeksN/A

General Description

The DS91M040 is a quad M-LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multi-point applications. Controlled transition times minimize reflections that are common in multipoint configurations due to unterminated stubs. M-LVDS devices also have a very large input common mode voltage range for additional noise margin in heavily loaded and noisy backplane environments.

A single DS91M040 channel is a half-duplex transceiver that accepts LVTTL/LVCMOS signals at the driver inputs and converts them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, BLVDS, M-LVDS, LVPECL and CML) and convert them to 3V LVCMOS signals. The DS91M040 supports both M-LVDS type 1 and type 2 receiver inputs.

Design Tools

TitleSize in Kbytes Date Click link below to Download    
DS91M040EVK Documentation 2 Kbytes 16-Apr-2008 View    

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

TitleSize in Kbytes Date Click link below to Download
AN-1926: Application Note 1926 An Introduction to M-LVDS and Clock and Data Distribution Applications 344 Kbytes 4-Dec-08 Download
AN-1503: Application Note 1503 Designing an ATCA Compliant M-LVDS Clock Distribution Network 2926 Kbytes 20-Nov-07 Download
AN-1503 (Chinese): Application Note 1503 Designing an ATCA Compliant M-LVDS Clock Distribution Network
 463 Kbytes  

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 3-Jul-2009]