Features • DC - 125 MHz / 250 Mbps low jitter, low skew, low power operation • Wide Input Common Mode Voltage Range allows up to ±1V of GND noise • Conforms to TIA/EIA-899 M-LVDS Standard • Pin selectable M-LVDS receiver type (1 or 2) • Controlled transition times (2.0 ns typ) minimize reflections • 8 kV ESD on M-LVDS I/O pins protects adjoining components • Flow-through pinout simplifies PCB layout • Small 5 mm x 5 mm LLP-32 space saving package Description The DS91M040 is a quad M-LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks. M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multi-point applications. Controlled transition times minimize reflections that are common in multipoint configurations due to unterminated stubs. M-LVDS devices also have a very large input common mode voltage range for additional noise margin in heavily loaded and noisy backplane environments. A single DS91M040 channel is a half-duplex transceiver that accepts LVTTL/LVCMOS signals at the driver inputs and converts them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, BLVDS, M-LVDS, LVPECL and CML) and convert them to 3V LVCMOS signals. The DS91M040 supports both M-LVDS type 1 and type 2 receiver inputs. Applications • Multidrop / Multipoint clock and data distribution • High-Speed, Low Power, Short-Reach alternative to TIA/EIA-485/422 • Clock distribution in AdvancedTCA (ATCA) and • MicroTCA (μTCA, uTCA) backplanes

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Typical Application *click for larger image	Block Diagram *click for larger image
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Datasheet

Title		Size	Date	Other Language
	DS91M040 125 MHz Quad M-LVDS Transceiver	419 Kbytes	9-Nov-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1926: Application Note 1926 An Introduction to M-LVDS and Clock and Data Distribution Applications	344 Kbytes	4-Dec-08	中文
	AN-1503: Application Note 1503 Designing an ATCA Compliant M-LVDS Clock Distribution Network	2926 Kbytes	20-Nov-07	中文

More Application Notes

Title		Size	Date	Other Language
	AN-971: Application Note 971 An Overview of LVDS Technology	168 Kbytes	5-Oct-98	日本語

Design Tools

Title	Size	Date
DS91M040EVK Documentation

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS91M040TSQ	CMOS7	0	18406	0	0	1089000	4	309006723
DS91M040TSQE	CMOS7	0	18406	0	0	1089000	4	309006723
DS91M040TSQX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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