Features • DC to 100+ MHz / 200+ Mbps low power, low EMI operation • Optimal for ATCA, uTCA clock distribution networks • Meets or exceeds TIA/EIA-899 M-LVDS Standard • Wide Input Common Mode Voltage for Increased Noise Immunity • DS91D180 has type 1 receiver input • DS91C180 has type 2 receiver input for fail-safe functionality • Industrial temperature range • Space saving SOIC-14 package (JEDEC MS-012) Description The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks. The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

Also Recommended DS91C180▲ For Version With MLVDS Type-2 (Control) Input With Failsafe And 100mV Offset DS91D176▲ For MLVDS Evaluation Kit MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image	Block Diagram *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair	413 Kbytes	9-Nov-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1503: Application Note 1503 Designing an ATCA Compliant M-LVDS Clock Distribution Network	2926 Kbytes	20-Nov-07	中文
	AN-1926: Application Note 1926 An Introduction to M-LVDS and Clock and Data Distribution Applications	344 Kbytes	4-Dec-08	中文

More Application Notes

Title		Size	Date	Other Language
	AN-971: Application Note 971 An Overview of LVDS Technology	168 Kbytes	5-Oct-98	日本語

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS91D180TMA	CMOS7	0	18406	0	0	1089000	4	309006723
DS91D180TMAX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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