DS90UR241 - 5-43MHz DC- Balanced 24-Bit LVDS Serializer

Datasheet	Packaging	Samples & Pricing	Eval. Boards	Reliability	Design Tools	Reference Designs	Models	Knowledge Base

Features

•	5 MHz–43 MHz embedded clock and DC-Balanced 24:1 and 1:24 data transmission
•	User defined pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
•	User selectable clock edge for parallel data on both Transmitter and Receiver
•	Supports AC-coupling data transmission
•	Individual power-down controls for both Transmitter and Receiver
•	Embedded clock CDR (Clock and Data Recovery) on Receiver and no source of reference clock required
•	All codes RDL (random data lock) to support live-pluggable applications
•	LOCK output flag to ensure data integrity at Receiver side
•	Balanced T_SETUP/T_HOLD between RCLK and RDATA on Receiver side
•	Adjustable PTO (progressive turn-on) LVCMOS outputs on Receiver to minimize EMI and SSO effects
•	@Speed BIST to validate LVDS transmission path
•	All LVCMOS inputs and control pins have internal pulldown
•	On-chip filters for PLLs on Transmitter and Receiver
•	48-pin TQFP package for Transmitter and 64-pin TQFP package for Receiver
•	Pure CMOS .35 µm process
•	Power supply range 3.3V ± 10%
•	Temperature range –40°C to +105°C
•	Greater than 8 kV HBM ESD structure
•	Meets ISO 10605 ESD and AEC-Q100 compliance
•	Backward compatible mode with DS90C241/DS90C124

General Description

The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. More...

Typical Application

*click for larger image

Parametric Table expand

Parametric Table collapse

Function Serializer

Color Depth 18 bpp

Pixel Clock Max 43 MHz

Pixel Clock Min 5 MHz

Compression Ratio 24:1

Input Compatibility LVCMOS

Output Compatibility FPD- Link II LVDS

Signal Conditioning Pre-emphasis, VOD Select

Function Serializer

Color Depth 18 bpp

Pixel Clock Max 43 MHz

Pixel Clock Min 5 MHz

Compression Ratio 24:1

Input Compatibility LVCMOS

Output Compatibility FPD- Link II LVDS

Signal Conditioning Pre-emphasis, VOD Select

AEC Q-100 Automotive Grade 2

Power Consumption_ 215 mW

Total Throughput 1032 Mbps

Payload/Channel 1032 Mbps

Reference Clock Req'd Deserializer No

Start/Stop Bit Yes

Embedded Clock Yes

Special Features Pre-Emphasis, DC Balance, VOD Select

Eval Kit SERDESUR-43USB

ESD 8 kV

Supply Voltage 3.3 Volt

Temperature Min -40 deg C

Temperature Max 105 deg C

Automotive Selection Guide Yes

DisplayType LCD

PowerWise No

Communications No

Sensing & Imaging Yes

Parallel Bus Width 24 bits

View Using Catalog

Also Recommended

DS90C124	Deserializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
DS90C241	Serializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
DS90UR124	Deserializer, 5-43 MHz, –40°C To +105°C, 10 Meter Drive Strength (FOR COMPLETE CHIPSET)
DS99R101	Serializer & DS99R102 Deserializer Chipset, 3-40 MHz, 0°C To +70°C, 2 Meter Drive Strength
DS99R103	Serializer & DS99R104 Deserializer Chipset, 3-40 MHz, -40°C To +85°C, 5 Meter Drive Strength
DS99R105	Serializer & DS99R106 Deserializer Chipset, 3-40 MHz, 0°C To +70°C, 10 Meter Drive Strength

Additional Resources

Design Tools (see below)

Connection Diagram

*click for larger image

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer	1091 Kbytes	8-Jan-08	Download
DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer (Japanese)	948 Kbytes

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Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

SERDESUR-43USB

Evaluation Kit for DS90UR241/DS90UR124 Serializer and Deserializer Chipset

Full production

N/A

$250.00

N/A

DS90UR241IVS

TQFP

NOPB

260

RoHS

N/A

Not recommended for new designs
(as of 15-Feb-08)

ds90ur241.ibs

1K+

$5.30

tray
of
250

NSUZXYTT
DS90UR24
1IVS

6 weeks

1000

DS90UR241QVS

TQFP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.30

tray
of
250

NSUZXYTT
DS90UR24
1QVS

6 weeks

500

DS90UR241IVSX

TQFP

NOPB

260

RoHS

N/A

Not recommended for new designs
(as of 15-Feb-08)

N/A

1K+

$5.30

reel
of
1000

NSUZXYTT
DS90UR24
1IVS

6 weeks

2000

DS90UR241QVSX

TQFP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$5.30

reel
of
1000

NSUZXYTT
DS90UR24
1QVS

6 weeks

15000

General Description

The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90UR241/124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90UR241IVS	CMOS7	0	16561	0	0	954000	4	270700104
DS90UR241IVSX	CMOS7	0	16561	0	0	954000	4	270700104
DS90UR241QVS	CMOS7	0	16561	0	0	954000	4	270700104
DS90UR241QVSX	CMOS7	0	16561	0	0	954000	4	270700104

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
LVDS Owner's Manual - 3rd Edition	2 Kbytes	4-Jan-2008	View
Evaluation Kit for DS90UR241/DS90UR124 Serializer and Deserializer Chipset			View

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Reference Designs

•	RD-167 - High Efficiency Portable Media Player (PMP) Docking Station

Application Notes

Title	Size in Kbytes	Date
AN-1898: Application Note 1898 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces	308 Kbytes	4-Sep-08	Download
AN-1826: Application Note 1826 Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers	251 Kbytes	24-Mar-08	Download
AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	Download
AN-1807: Application Note 1807 FPD-Link II Display SerDes Overview	102 Kbytes	14-May-08	Download

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[Information as of 3-Jul-2009]