Embedded clock with DC Balancing supports AC-coupled data transmission
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Capable to drive up to 10 meters shielded twisted-pair cable
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No reference clock required (deserializer)
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Meets ISO 10605 ESD - Greater than 8 kV HBM ESD structure
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Hot plug support
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EMI Reduction - Serializer accepts spread spectrum input; data randomization and shuffling on serial link; Deserializer provides
Adjustable PTO (progressive turn-on) LVCMOS outputs
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@Speed BIST (built-in self test) to validate LVDS transmission path
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Individual power-down controls for both Transmitter and Receiver
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Power supply range 3.3V ± 10%
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48-pin TQFP package for Transmitter and 64-pin TQFP package for Receiver
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Temperature range -40°C to +105°C
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Backward compatible mode with DS90C241/DS90C124
Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream
with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color
depth - RGB666 + HS, VS, DE + 3 additional general purpose data channels. This single serial stream simplifies transferring
a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system
cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90UR241/124 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low power and
low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output
edge rate for the operating frequency range EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced
encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the
Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK.
The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.
The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. The DS90UR124 Deserializer board accepts the FPD-Link II LVDS serialized data stream and converts the data back into parallel LVCMOS signals and clock. USB cable is provided as a generic medium for the high speed data link. Jumpers and switches on the boards can be configured for evaluation of chipset features such as pre-emphasis, randomizer, @ BIST (built in system test), edge rate, current slew, Progressive Turn On.
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
DS90UR241
DS90C124
