Features • Low jitter 400 Mbps fully differential data path • 145 ps (typ) of pk-pk jitter with PRBS = 2 23−1 data pattern at 400 Mbps • Single +3.3 V Supply • Balanced output impedance • Output channel-to-channel skew is 35ps (typ) • Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load. • LVDS receiver inputs accept LVPECL signals • LVDS input failsafe • Fast propagation delay of 2.8 ns (typ) • Receiver open, shorted, and terminated input failsafe • 28 lead TSSOP package • Conforms to ANSI/TIA/EIA-644 LVDS standard Description DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the Application Information section of this datasheet.

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Typical Application *click for larger image	Block Diagram click for larger image
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Datasheet

Title		Size	Date	Other Language
	DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe	1248 Kbytes	19-Sep-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1926: Application Note 1926 An Introduction to M-LVDS and Clock and Data Distribution Applications	344 Kbytes	4-Dec-08	中文

More Application Notes

Title		Size	Date	Other Language
	AN-971: Application Note 971 An Overview of LVDS Technology	168 Kbytes	5-Oct-98	日本語

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90LV110ATMT	CMOS7	0	18406	0	0	1089000	4	309006723
DS90LV110ATMTX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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