Features • Single +3.3 V Supply • LVDS receiver inputs accept LVPECL signals • TRI-STATE outputs • Receiver input threshold < ±100 mV • Fast propagation delay of 1.4 ns (typ) • Low jitter 800 Mbps fully differential data path • 100 ps (typ) of pk-pk jitter with PRBS = 2 23−1 data pattern at 800 Mbps • Compatible with ANSI/TIA/EIA-644-A LVDS standard • 8 pin SOIC and space saving (70%) LLP package • Industrial Temperature Range Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance. A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator. An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE. The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC.

Also Recommended DS10BR150▲ Low Jitter, Low Power LVDS Buffer DS90LV804▲ Quad Version MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image	Block Diagram click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS90LV001 800 Mbps LVDS Buffer	511 Kbytes	19-Feb-08	日本語

Featured Application Notes

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More Application Notes

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Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90LV001TLD	CMOS7	0	18406	0	0	1089000	4	309006723
DS90LV001TLDX	CMOS7	0	18406	0	0	1089000	4	309006723
DS90LV001TM	CMOS7	0	18406	0	0	1089000	4	309006723
DS90LV001TMX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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