Features • Up to 6.384 Gbps throughput • 66MHz to 133MHz input clock support • Reduces cable and connector size and cost • Cable Deskew function • DC balance reduces ISI distortion • For point-to-point backplane or cable applications • Low power, 890 mW typ at 133MHz • Flow through pinout for easy PCB design • +3.3V supply voltage • 100-pin TQFP package • Conforms to TIA/EIA-644-A-2001 LVDS Standard Description The DS90CR486 receiver converts eight Low Voltage Differential Signaling (LVDS) data streams back into 48 bits of LVCMOS/LVTTL data. Using a 133MHz clock, the data throughput is 6.384Gbit/s (798Mbytes/s). The multiplexing of data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in interconnect width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The DS90CR486 deserializer is improved over prior generations of Channel Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum clock rate is increased to 133 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis (on DS90CR485) feature that provides additional output current during transitions to counteract cable loading effects. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew. These three enhancements allow long cables to be driven. The DS90CR486 is intended to be used with the DS90CR485 Channel Link Serializer. It is also backward compatible with serializers DS90CR481 and DS90CR483. The DS90CR486 is footprint compatible with the DS90CR484. The chipset is an ideal solution to solve EMI and interconnect size problems for high-throughput point-to-point applications. For more details, please refer to the “Applications Information” section of this datasheet.

Also Recommended DS90CR485▲ 133Mhz LVDS 48-Bit Channel Link Serializer MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

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Datasheet

Title		Size	Date	Other Language
	DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)	361 Kbytes	17-Nov-06	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1538: Application Note 1538 Interfacing National’s DS90CR218A and LM98714	280 Kbytes	17-Mar-07	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1538: Application Note 1538 Interfacing National’s DS90CR218A and LM98714	280 Kbytes	17-Mar-07	中文

Design Tools

Title	Size	Date
Channel Link Design Guide	3173 Kbytes	29-Mar-2007
48-bit Channel Link Serializer / Deserializer Evaluation Board 133MHz

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CR486VS	.35	0	19690	0	0	1425000	3	404347640
DS90CR486VSX	.35	0	19690	0	0	1425000	3	404347640

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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