Features Up to 6.384 Gbps throughput 66MHz to 133MHz input clock support Reduces cable and connector size and cost Pre-emphasis reduces cable loading effects DC balance reduces ISI distortion 24 bit double edge inputs 3V Tolerant LVCMOS/LVTTL inputs Low power, 2.5V supply Flow-through pinout In 100-pin TQFP package Conforms with TIA/EIA-644-A LVDS standard. Description The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phase-locked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost. The double edge input strobes data on both the rising and falling edges of the clock. This minimizes the pin count required and simplifies PCB routing between the host chip and the serializer. This chip is an ideal solution to solve EMI and interconnect size problems for high throughput point-to-point applications. The DS90CR485 is intended for use with the DS90CR486 Channel-Link receiver. It is also backward compatible with other Channel-Link receiver such as the DS90CR482 and DS90CR484. For more details, please refer to the "Applications Information" section of this datasheet.

Also Recommended DS90CR486▲ 133Mhz LVDS 48-Bit Channel Link Deserializer

	Block Diagram click for larger image

Parameters / Values	DS90CR485	DS90CR486
Function	Serializer	Deserializer
Total Throughput	6384 Mbps	6384 Mbps
Payload/Channel	798 Mbps	798 Mbps
Clock Min	66 MHz	66 MHz
Clock Max	133 MHz	133 MHz
Input Compatibility	LVTTL	LVDS
Output Compatibility	LVDS	LVTTL
Power Consumption_	585 mW	439 mW
SupplyVoltage	2.5 Volt	3.3 Volt
Eval Kit	CLINK3V48BT-133	CLINK3V48BT-133
ESD	2 kV	2 kV
Temperature Min	-10 deg C	-10 deg C
Temperature Max	70 deg C	70 deg C
Compression Ratio	48:8	48:8
Number Transmitters	1
Sensing & Imaging	Yes	Yes
Parallel Bus Width	48 bits	48 bits

Datasheets

Title		Size	Date	Other Language
	DS90CR485 133MHz LVDS 48-bit Channel Link Serializer	330 Kbytes	6-Oct-03	日本語

Application Notes

Title		Size	Date	Other Language
	AN-1041: Application Note 1041 Channel Link Moving and Shaping Information in Point[hyphen]to[hyphen]Point Applications	230 Kbytes	4-Oct-04
	AN-1108: Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines	205 Kbytes	4-Oct-04
	AN-1109: Application Note 1109 Multi-Drop Channel-Link Operation	173 Kbytes	4-Oct-04

Other Technical Documents

Title		Type	Date
	Channel Link I Design Guide	Design Guide	2007-03-29
	The Many Flavors of LVDS	Technology Edge	2002-02-01

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
DS90CR485VS/NOPB DS90CR485VS RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty AVNET-EM Worldwide 120 DIGI-KEY Worldwide 135 MOUSER Worldwide 90	$12.90 each at 1K+ pcs	tray of 90
DS90CR485VSX/NOPB DS90CR485VSX RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty DIGI-KEY Worldwide 0	$12.90 each at 1K+ pcs	reel of 1000

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR485.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR485 is located at RoHS Status.

Part Number(s) (NSID)	Description	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
CLINK3V48BT-133	48-bit Channel Link Serializer / Deserializer Evaluation Board 133MHz	Preliminary	Distributor Region Qty DIGI-KEY Worldwide 0	$500.00 each	1
Description: The CLINK3V48BT-133 evaluation kit demonstrates the performance of the DS90CR485/485 48-bit, 66 - 133 MHz Channel Link SerDes chipset. The transmitter serializes 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phase-locked clock is also transmitted in parallel with the data streams over a 9th LVDS pair. The receiver converts the 8 LVDS data streams plus clock back to 48 LVCMOS/LVTTL data bits plus clock. Contents: CLINK3V485/486 PCB with DS90CR485VS Transmitter and DS90CR486VS Receiver One 2-meter 3M MDR LVDS cable interface Evaluation Kit Documentation DS90CR485/DS90CR486 Datasheet What the user needs to provide: The users need to provide 3.3V and/or a 2.5V supply. The device in this kit can be configured to generate its own LVDS data (PRBS-15 and PRBS-23). However, if users want to do BERT on the whole system, they will need to have equipment to send 24 bits of parallel DDR LVCMOS data + 1 Tx clock as well as receive 48 bits of parallel LVCMOS data + 1 Rx clock. If desired, users can use a Tx board from another CLINK kit to avoid using the DDR interface on the serializer in the CLINK3V48BT-133 kits.

National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C1) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/en/packaging/greennopb.html. Lead free products are RoHS compliant.

Lead Free product status is available through the search tool located here

Part Number(s) (NSID)	Weight (milligrams)	Type	Pins	MSL Rating	Peak Reflow	RoHS Status	CAD Symbols	Models	Package Marking Format
DS90CR485VS/NOPB DS90CR485VS	508.38 510.01	TQFP	100	3 3	260 260	Detail	Download	ibis file	NSUZXYYTTE# DS90CR485VS BBBBB
DS90CR485VSX/NOPB DS90CR485VSX	508.38 510.01	TQFP	100	3 3	260 260	Detail	Download	N/A	NSUZXYYTTE# DS90CR485VS BBBBB

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR485.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR485 is located at RoHS Status.

Design Tools

Title	Size	Date
Channel Link Design Guide
48-bit Channel Link Serializer / Deserializer Evaluation Board 133MHz

CAD Symbols and Models Download DS90CR485 CAD Symbols

Models ibis file

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CR485VS	CMOS8	1	13725	73	0	1774500	2	503519220
DS90CR485VSX	CMOS8	1	13725	73	0	1774500	2	503519220

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR485.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR485 is located at RoHS Status.