Features 3.168 Gbits/sec bandwidth with 66 MHz Clock 5.376 Gbits/sec bandwidth with 112 MHz Clock 65 - 112 MHz input clock support LVDS SER/DES reduces cable and connector size Pre-emphasis reduces cable loading effects Optional DC balance encoding reduces ISI distortion Cable Deskew of +/-1 LVDS data bit time (up to 80 MHz Clock Rate) 5V Tolerant TxIN and control input pins Flow through pinout for easy PCB design +3.3V supply voltage Transmitter rejects cycle-to-cycle jitter Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard Description The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled and transmitted. The DS90CR482 receiver converts the LVDS data streams back into 48 bits of LVCMOS/TTL data. At a transmit clock frequency of 112MHz, 48 bits of TTL data are transmitted at a rate of 672Mbps per LVDS data channel. Using a 112MHz clock, the data throughput is 5.38Gbit/s (672Mbytes/s). At a transmit clock frequency of 112MHz, 48 bits of TTL data are transmitted at a rate of 672Mbps per LVDS data channel. Using a 66MHz clock, the data throughput is 3.168Gbit/s (396Mbytes/s). The multiplexing of data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 48 CMOS/TTL inputs can support a variety of signal combinations. For example, 6 8-bit words or 5 9-bit (byte + parity) and 3 controls. The DS90CR481/DS90CR482 chipset is improved over prior generations of Channel Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/-1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

	Block Diagram click for larger image

Parameters Values Function Serializer Total Throughput 5376 Mbps Payload/Channel 672 Mbps Clock Min 65 MHz Clock Max 112 MHz Input Compatibility LVTTL Output Compatibility LVDS Power Consumption_ 512 mW SupplyVoltage 3.3 Volt ESD 6 kV Temperature Min -10 deg C Temperature Max 70 deg C Compression Ratio 48:8 Number Transmitters 1 Sensing & Imaging Yes Parallel Bus Width 48 bits

Datasheets

Title		Size	Date	Other Language
	DS90CR481 48-Bit LVDS Channel Link Serializer - 65 - 112 MHz	904 Kbytes	31-Jan-06	日本語

Application Notes

Title		Size	Date	Other Language
	AN-1041: Application Note 1041 Channel Link Moving and Shaping Information in Point[hyphen]to[hyphen]Point Applications	230 Kbytes	4-Oct-04
	AN-1108: Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines	205 Kbytes	4-Oct-04
	AN-1109: Application Note 1109 Multi-Drop Channel-Link Operation	173 Kbytes	4-Oct-04

Other Technical Documents

Title		Type	Date
	Channel Link I Design Guide	Design Guide	2007-03-29
	Eye Opening Enhancements extend the reach of high-speed Interfaces	Technology Edge	2002-10-01
	The Many Flavors of LVDS	Technology Edge	2002-02-01

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
DS90CR481VJD/NOPB DS90CR481VJD RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty ARROW Worldwide 90 DIGI-KEY Worldwide 0 MOUSER Worldwide 90 TAYLOR Americas 170	$9.50 each at 1K+ pcs	tray of 90

Obsolete Versions

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
DS90CR481VJDX	NONE	NATIONAL SEMICONDUCTOR	16 Nov 2008

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR481.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR481 is located at RoHS Status.

Part Number(s) (NSID)	Description	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
CLINK3V48BT-112	48-bit Channel Link Serializer / Deserializer Evaluation Board 112MHz	Preliminary	Distributor Region Qty DIGI-KEY Worldwide 0	$500.00 each	1
Description: This Channel Link demo kit contains a transmitter (Tx) demo board and a receiver (Rx) demo board along with an interface cable. This kit will demonstrate the chipsets transmitting data streams using Low Voltage Differential Signaling (LVDS) through a cable at seven times the input clock rate. The transmitter board accepts 3V TTL/CMOS data signals from an incoming data source along with the clock signal. The LVDS transmitter converts the TTL/CMOS parallel lines into serialized LVDS pairs. The serial data streams toggle at 7 times the clock speed. The receiver board accepts the LVDS serialized data (and clock) and converts them back into parallel 3V TTL/CMOS data out signals. Contents: One Transmitter board with IDC connectors on Tx input DS90CR483MTD - 48 bit Transmitter One Receiver board with IDC connectors on Rx output DS90CR484MTD - 48 bit Receiver One 2-meter 3M MDR LVDS Cable interface to connect TxOUT to RxIN. Note: The MDR footprint has been set to accept a D26-1 pinout. Demonstration Kit Documentation DS90CR483A/DS90CR484A Datasheet What the user needs to provide: 3.3V supply Equipment to transmit for 48 parallel LVCMOS bits + 1 Tx clock For BERT, receiver for 48 parallel LVCMOS data + 1 Rx clock

National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C1) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/en/packaging/greennopb.html. Lead free products are RoHS compliant.

Lead Free product status is available through the search tool located here

Part Number(s) (NSID)	Weight (milligrams)	Type	Pins	MSL Rating	Peak Reflow	RoHS Status	CAD Symbols	Models	Package Marking Format
DS90CR481VJD/NOPB DS90CR481VJD	508.38 510.01	TQFP	100	3 3	260 260	Detail	Download	N/A	NS2ZXYYTTE# DS90CR481VJD BBBBB

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR481.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR481 is located at RoHS Status.

Design Tools

Title	Size	Date
Channel Link Design Guide
48-bit Channel Link Serializer / Deserializer Evaluation Board 112MHz

CAD Symbols and Models Download DS90CR481 CAD Symbols

Models N/A

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CR481VJD	.35	0	20275	0	0	1515000	3	429885386

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CR481.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CR481 is located at RoHS Status.

Obsolete Versions

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
DS90CR481VJDX	NONE	NATIONAL SEMICONDUCTOR	16 Nov 2008