DS90CR218A - +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 85 MHz

Datasheet Packaging Samples & Pricing Reliability Models Knowledge Base

Features
•12 to 85 MHz shift clock support
•50% duty cycle on receiver output clock
•Low power consumption
•±1V common-mode range (around +1.2V)
•Narrow bus reduces cable size and cost
•Up to 1.785 Gbps throughput
•Up to 223 Mbytes/sec bandwidth
•345 mV (typ) swing LVDS devices for low EMI
•PLL requires no external components
•Rising edge data strobe
•Compatible with TIA/EIA-644 LVDS standard
•Low profile 48-lead TSSOP package

General Description

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. More...


  Typical Application
click for larger image


Parametric Table     expand
Parametric Table    collapse
Function Deserializer
Total Throughput 1785 Mbps
Payload/Channel 595 Mbps
Clock Min 12 MHz
Clock Max 85 MHz
Compression Ratio 21:3
Function Deserializer
Total Throughput 1785 Mbps
Payload/Channel 595 Mbps
Clock Min 12 MHz
Clock Max 85 MHz
Input Compatibility LVDS
Output Compatibility LVTTL
Power Consumption_ 297 mW
SupplyVoltage 3.3 Volt
Eval Kit CLINK3V28BT-85
ESD 7 kV
Temperature Min -10 deg C
Temperature Max 70 deg C
Compression Ratio 21:3
Number Receivers 1
Sensing & Imaging Yes
Parallel Bus Width 21 bit
View Using Catalog

  Block Diagram
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Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz 616 Kbytes 19-Oct-06 View Online
Download
DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz (Japanese)
 403 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
CLINK3V28BT-8528-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHzPreliminaryN/A
 
Buy Now 		1+$500.001-
N/AN/A
DS90CR218AMTDTSSOP48STD
NOPB		2
2		235
260		RoHS Download Full production
90cr218a.ibs		Samples
Buy Now 		1K+$3.50rail
of
38		NSUZXYTT
DS90CR218AMTD
BBBBB
6 weeks500
DS90CR218AMTDXTSSOP48NOPB2260RoHS Download Full productionN/A
 
Buy Now 		1K+$3.50reel
of
1000		NSUZXYTT
DS90CR218AMTD
BBBBB
6 weeks5000

General Description

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM * LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90CR218AMTDCMOS7013906008625005244736730
DS90CR218AMTDXCMOS7013906008625005244736730

Note: The Early Failure Rates were calculated as point estimates. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Application Notes

TitleSize in Kbytes Date Click link below to Download
AN-1538: Application Note 1538 Interfacing National’s DS90CR218A and LM98714 280 Kbytes 17-Mar-07 Download
AN-1538 (Chinese): Application Note 1538 Interfacing National’s DS90CR218A and LM98714
 281 Kbytes  

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[Information as of 21-Nov-2008]