Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
 |
| DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz |
616 Kbytes |
19-Oct-06 |
Download |
DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz (Japanese)
 |
403 Kbytes |
|
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Package Availability, Models, Samples & Pricing
General Description
The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
|
DS90CR218AMTD | CMOS7 | 0 | 16561 | 0 | 0 | 954000 | 4 | 270700104
|
|
DS90CR218AMTDX | CMOS7 | 0 | 16561 | 0 | 0 | 954000 | 4 | 270700104
|
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
Design Tools
| Title | Size in Kbytes |
Date |
|
|
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| 28-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHz |
|
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View |
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Application Notes
| Title | Size in Kbytes |
Date |
|
| AN-1538: Application Note 1538 Interfacing National’s DS90CR218A and LM98714 |
280 Kbytes |
17-Mar-07 |
Download |
AN-1538 (Chinese): Application Note 1538 Interfacing National’s DS90CR218A and LM98714
|
281 Kbytes |
|
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[Information as of 5-Jul-2009]
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