DS90CR217 - +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Transmitter - 85 MHz
Datasheet Packaging Samples & Pricing Reliability Design Tools Models Knowledge Base

Features
•20 to 85 MHz shift clock support
•50% duty cycle on receiver output clock
•Best-in-Class Set & Hold Times on TxINPUTs
•Low power consumption
•±1V common-mode range (around +1.2V)
•Narrow bus reduces cable size and cost
•Up to 1.785 Gbps throughput
•Up to 223 Mbytes/sec bandwidth
•345 mV (typ) swing LVDS devices for low EMI
•PLL requires no external components
•Rising edge data strobe
•Compatible with TIA/EIA-644 LVDS standard
•Low profile 48-lead TSSOP package

General Description

The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. More...


  Typical Application
click for larger image


ParametersValues
Function Serializer
Total Throughput 1785 Mbps
Payload/Channel 595 Mbps
Clock Min 20 MHz
Clock Max 85 MHz
Input Compatibility LVTTL
Output Compatibility LVDS
Power Consumption_ 128.7 mW
SupplyVoltage 3.3 Volt
Eval Kit CLINK3V28B-85
ESD 7 kV
Temperature Min -10 deg C
Temperature Max 70 deg C
Compression Ratio 21:3
Number Transmitters 1
Sensing & Imaging Yes
Parallel Bus Width 21 bits

  Additional Resources
Design Tools


Block Diagram

click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz 625
Kbytes		 19-Oct-06 Download
DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz (Japanese)
 325 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
CLINK3V28BT-8528-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHzPreliminaryN/A
 
Buy Now 		1+$500.001-
N/AN/A
DS90CR217MTDTSSOP48NOPB
STD		2
2		260
235		RoHS Download Full production
90cr217.ibs		Samples
Buy Now 		1K+$4.00rail
of
38		NS2ZXYTTE#
DS90CR217MTD
BBBBB
6 weeks500
DS90CR217MTDXTSSOP48NOPB2260RoHS Download Full productionN/A
 
Buy Now 		1K+$4.00reel
of
1000		NS2ZXYTTE#
DS90CR217MTD
BBBBB
6 weeks2000

General Description

The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90CR217MTD.350196900014250003404347640
DS90CR217MTDX.350196900014250003404347640

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Design Tools

TitleSize in Kbytes Date Click link below to Download    
Channel Link Design Guide 3173 Kbytes 29-Mar-2007 View Online Download  
28-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHz     View    

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[Information as of 8-Nov-2009]