Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
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| DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz |
625 Kbytes |
19-Oct-06 |
Download |
DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz (Japanese)
 |
325 Kbytes |
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Package Availability, Models, Samples & Pricing
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
|
DS90CR217MTD | .35 | 0 | 19690 | 0 | 0 | 1425000 | 3 | 404347640
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DS90CR217MTDX | .35 | 0 | 19690 | 0 | 0 | 1425000 | 3 | 404347640
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Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
Design Tools
| Title | Size in Kbytes |
Date |
 |
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| Channel Link Design Guide |
3173 Kbytes |
29-Mar-2007 |
View Online |
Download |
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| 28-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHz |
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View |
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[Information as of 8-Nov-2009]
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