Features • Single +3.3V supply • Chipset (Tx + Rx) power consumption <250 mW (typ) • Power-down mode (<0.5 mW total) • Up to 173 Megabytes/sec bandwidth • Up to 1.386 Gbps data throughput • Narrow bus reduces cable size • 290 mV swing LVDS devices for low EMI • +1V common mode range (around +1.2V) • PLL requires no external components • Low profile 48-lead TSSOP package • Rising edge data strobe • Compatible with TIA/EIA-644 LVDS standard • ESD Rating > 7 kV • Operating Temperature: −40°C to +85°C Description The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.

Also Recommended DS90CR217▲ 85 Mhz Transmit Clock Frequency MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz	434 Kbytes	7-Jun-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map	13 Kbytes	15-May-04
	AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04

More Application Notes

Title		Size	Date	Other Language
	AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04
	AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map	13 Kbytes	15-May-04

Design Tools

Title	Size	Date
Channel Link Design Guide	3173 Kbytes	29-Mar-2007
28-Bit Channel Link Serializer / Deserializer Evaluation Board 20-85MHz

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CR215MTD	.35	0	19690	0	0	1425000	3	404347640
DS90CR215MTDX	.35	0	19690	0	0	1425000	3	404347640

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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